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yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 3 o verview the single-chip pci express based 88E8053 device integrates the marvell ? market-leading gigabit phy with the proven marvell gigabit mac and serdes cores, delivering an ultra-sma ll form factor and high per- formance. delivered with the industry?s most compre- hensive software driver suite, this yukon device is ideally suited for lan on motherboard (lom) and net- work interface card (nic) applications. the 88E8053 device is compliant with the pci express 1.0a specifica- tion. offered in a 9 x 9 mm, 64-pin qfn package, the 88E8053 reduces board space required for gigabit lom implementation significantly. the device is optimized for maximum throughput and low cpu utilization. a 48 kb on-chip buffer eliminates the need for any external memory. packet processing tasks such as tcp segmentat ion, vlan insertion and removal, tcp/udp/ip che cksum calculation and check- ing are all performed on-chip. these offloads along with interrupt moderation schemes reduce cpu utilization and improve the overal l system performance. the 88E8053 device incorporates advanced power management schemes, enabling energy efficient opera- tion. with features such as wake on lan and smart power down in the absence of link it is well suited for client applications including mobile pcs. the 88E8053 yukon device incorporates the marvell virtual cable tester? (vct?) technology for advanced cable diagnostics. vct enables it managers to pinpoint the location of cabling issues down to a meter or less, reducing network installation and support costs. the device comes with a comprehensive suite of soft- ware device drivers for a ll desktop operating systems, including microsoft? windows? 98/me, nt, 2000, and xp, linux, and novell netware. a complete hardware reference design is provided for a quick implementation. f eatures pci e xpress features ? pci express base specification 1.0a compliant ? x1 pci express interface with 2.5 ghz signaling ? active state power management (l0s) support ? advanced error reporting mac / phy features ? configurable 48 kb deep buffer ? descriptor bursting and caching ? message signaled interrupts ? tcp segmentation offload / large-send support ? on-chip vlan inse rtion and removal ? tcp, ip, udp checksum offload ? interrupt moderation ? jumbo frame support ? compliant to 802.3x flow control support ? ieee 802.1p and 802.1q support ? 10/100/1000 ieee 802.3 compliant ? automatic mdi/mdix crossover at all speeds m anageability ? wake on lan (wol) power management support ? compliant to acpi 2.0 specification ? out of the box wol support ? wake on link ? serial peripheral interfac e (spi) for remote boot (pxe 2.1) ? smart power down when link is not detected ? marvell virtual cable tester? (vct) for advanced cable diagnostics o ther f eatures ? lom disable pin ? power regulator outputs for 2.5v and 1.2v supplies ? two wire serial interface (twsi) for vpd eeprom ? 9 mm x 9 mm, 64-pin qfn package marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00,rev. -- confidential copyright ? 2004 marvell page 4 document classification: proprieta ry information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table of contents s ection 1. s ignal d escription .............. .............. .............. .............. ........... 7 1.1 64-pin qfn pinout (top view) ...................................................................................... 7 1.2 pin description ............................................................................................................. .8 1.2.1 pin type definitions ...................................................................................................... ...... 8 s ection 2. f unctional d escription ............... ................ ............... ........... 14 2.1 overview.................................................................................................................... ... 14 2.2 pci-express features.................................................................................................. 16 2.3 spi flash memory........................................................................................................ 18 2.4 spi flash memory loader........................................................................................... 20 2.5 twsi eeprom ................ ................ ................ ................. ................ ................ ............ 22 2.6 twsi eeprom loader ............. ................ ................ ................ ............. ............. ......... 23 2.7 plug in go unit............................................................................................................. 24 2.8 interrupts .................................................................................................................. .... 25 2.8.1 irq moderation time r ...................................................................................................... 27 2.8.2 message signaled interrupts (m si) .................................................................................. 28 2.9 buffer management units (bmu)................ ................................................................ 28 2.9.1 format of descriptor and status list element s ................................................................ 28 2.9.2 tcp/udp processing of rx and tx bmu........................................................................ 39 2.9.3 prefetch unit ............................................................................................................. ........ 40 2.9.4 status bmu................................................................................................................ ....... 41 2.9.5 polling unit.......... .............. .............. .............. .............. ........... ........... ........... ........... .......... 45 2.10 timer ...................................................................................................................... ....... 46 2.11 timestamp timer ......................................................................................................... 46 2.12 wake on lan................................................................................................................ 47 2.12.1 wake up frame logic...................................................................................................... .47 2.12.2 magic packet frame detect ............................................................................................... 4 9 2.12.3 link change monitoring ................................................................................................... .49 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 5 2.13 gmac ....................................................................................................................... ..... 50 2.14 phy........................................................................................................................ ........ 51 2.15 leds ....................................................................................................................... ....... 51 2.15.1 led capabilities of 88E8053...... .............. .............. .............. .............. ........... ........... ........ 51 2.16 vpd....................................................................................................................... ........ 52 2.17 twsi interface ............................................................................................................. .52 2.18 parity generation/check ............................................................................................ 52 2.18.1 internal byte based parity checking/generatin g .......... .............. .............. .............. ........... 52 2.18.2 parity checking/generating on pci as targ et.................................................................. 53 2.18.3 parity checking/generating on pci as master ............ .............. .............. .............. ........... 53 s ection 3. r egister d escription ................ ................. ................ .............54 3.1 legend ...................................................................................................................... .... 54 3.2 pci-express configuration register file................................................................... 55 3.2.1 overview and address map ............................. ................................................................ 55 3.2.2 registers of pci header re gion ...................................................................................... 58 3.2.3 registers of header region . .............. .............. .............. .............. .............. .............. ........ 59 3.2.4 registers of device dependent region ........... .............. .............. .............. .............. ........ 69 3.3 control register file.................................................................................................. 108 3.3.1 overview and address map ............................. .............................................................. 108 3.3.2 registers ................................................................................................................. ....... 127 3.4 gmac registers......................................................................................................... 213 3.4.1 mac register definitions ........................... .................................................................... 213 s ection 4. e lectrical s pecifications ............. .............. .............. ...........239 4.1 absolute maximum ratings ...................................................................................... 239 4.2 recommended operating conditions........... ........................................................... 240 4.3 package thermal information ................................................................................... 241 4.3.1 thermal conditions for 64-pin qfn package...... ........................................................... 241 4.4 dc electrical characteristics .................................................................................... 242 4.4.1 current consumption avddl ........................................................................................ 242 4.4.2 current consumption vdd............................................................................................. 242 4.4.3 current consumption vddo_ttl.................................................................................. 243 4.4.4 digital operating conditions........................................................................................... 244 4.4.5 ieee dc transceiver paramete rs.............. .............. .............. ............ ........... ........... ...... 245 4.5 ac timing reference values .................................................................................... 246 4.6 ac electrical specifications...................................................................................... 247 4.6.1 reset timing .............................................................................................................. .... 247 4.6.2 device wakeup timing................................................................................................... 248 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00,rev. -- confidential copyright ? 2004 marvell page 6 document classification: proprieta ry information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 4.6.3 clock timing.............................................................................................................. ..... 249 4.6.4 pci express timing........................................................................................................ 250 4.6.5 two-wire serial interface (twsi) timing....................................................................... 252 4.6.6 spi flash memory interface timing .............................................................................. 253 4.6.7 smbus specifications.................................................................................................... 25 5 4.7 ieee ac parameters.... ................ ................ ................ ............. ............. ............. ........256 s ection 5. m echanical d rawings ................ ................ .............. ............ 257 5.1 64-pin qfn package...................................................................................................257 s ection 6. o rder i nformation ................ ................ ................. .............. 259 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 7 signal description 64-pin qfn pinout (top view) section 1. signal description 1.1 64-pin qfn pinout (top view) the 88E8053 device is manufactured in a 64-pin qfn, 9 x 9 mm package. figure 1: 88E8053 64-pin qfn package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 88E8053 top view 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 tstpt avddl mdin[2] mdip[2] hsdacn avdd avddl mdin[1] mdip[1] avddl mdin[0] mdip[0] hsdacp mdip[3] mdin[3] avddl avddl rx_n rx_p refclkp refclkn led_actn vddo_ttl led_link1000n led_linkn vdd25 avddl avddl tx_n tx_p 17 18 19 20 21 22 23 24 25 26 30 31 32 27 28 29 64 63 62 61 60 59 58 57 56 55 51 50 49 54 53 52 vddo_ttl vdd ctrl12 ctrl25 waken vdd vddo_ttl switch_vaux lom_disablen xtalo xtali rset perstn switch_vcc vaux_avlbl vdd vdd vmain_avlbl testmode vddo_ttl nc nc vpd_data vddo_ttl vdd spi_di spi_do vdd vdd vpd_clk spi_clk spi_cs led_link10/100n vdd 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 8 document classification: proprieta ry information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 1.2 pin description 1.2.1 pin type definitions pin type definition h input with hysteresis i/o input and output i input only o output only pu internal pull-up pd internal pull-down d open drain output z tri-state output ma dc sink capability marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 9 signal description pin description table 1: pci express signals 88E8053 pin # pin name pin type description 49 50 tx_p tx_n o analog pci express transmit line (positive and negative pair). 2.5 ghz low-voltage pair. 54 53 rx_p rx_n i analog pci express receive line (positive and negative pair). 2.5 ghz low-voltage pair. 6 waken o pci express wake signal. driven low to re-activate the pci express lin hiearchy?s main power rails and reference clocks. (open collector, active low.) multiplexed to the same pin as pci signal pmen. 55 56 refclkp refclkn i analog pci express platform reference clock (differential pair of positive and negative signal lines). 100 mhz low-voltage interface. 5 perstn i pci express fundamental reset. asserted 100 ms after power rails are within specifications. marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 10 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table 2: media dependent interface (phy) 88E8053 pin # pin name pin type description 17 18 mdip[0] mdin[0] i/o, d media dependent interfacepositive/negative[0]. in 1000base-t mode in mdi configuration, mdip/n[0] correspond to bi_dap/n. in mdix configuration, mdip/n[0] correspond to bi_dbp/ n. in 100base-tx and 10b ase-t modes in mdi configuration, mdip/ n[0] are used for the transmit pair. in mdix configuration, mdip/n[0] are used for the receive pair. mdip/n[0] should be tied to ground if not used. 20 21 mdip[1] mdin[1] i/o, d media dependent interfacepositive/negative[1]. in 1000base-t mode in mdi configuration, mdip/n[1] correspond to bi_dap/n. in mdix configuration, mdip/n[1] correspond to bi_dbp/ n. in 100base-tx and 10b ase-t modes in mdi configuration, mdip/ n[1] are used for the transmit pair. in mdix configuration, mdip/n[1] are used for the receive pair. mdip/n[1] should be tied to ground if not used. 26 27 mdip[2] mdin[2] i/o, d media dependent interfacepositive/negative[2]. in 1000base-t mode in mdi configuration, mdip/n[2] correspond to bi_dap/n. in mdix configuration, mdip/n[2] correspond to bi_dbp/ n. in 100base-tx and 10base-t modes, mdip/n[2] are not used. mdip/n[2] should be tied to ground if not used. 30 31 mdip[3] mdin[3] i/o, d media dependent interfacepositive/negative[3]. in 1000base-t mode in mdi configuration, mdip/n[3] correspond to bi_dap/n. in mdix configuration, mdip/n[3] correspond to bi_dbp/ n. in 100base-tx and 10base-t modes, mdip/n[3] are not used. mdip/n[3] should be tied to ground if not used. marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 11 signal description pin description table 3: twsi interface (for connection to twsi eeprom) 88E8053 pin # pin name pin type description 38 vpd_clk o, d, pu twsi bus clock line to serial eeprom (with vpd/boot data). vpd_clk contains an internal pull-up resistor. 41 vpd_data bi-dir, pu twsi bus data line to serial eeprom (with vpd/boot data). vpd_data contains an internal pull-up resistor. table 4: spi flash memory interface 88E8053 pin # pin name pin type description 34 spi_do o data line leading to the spi flash memory. spi_do contains an internal pull-up resistor. 35 spi_di i data line coming from the spi flash memory. spi_di contains an internal pull-up resistor. 37 spi_clk o clock line for spi interface. spi_clk contains an internal pull-up resistor. 36 spi_cs o chip select for spi flash memory. spi_cs contains an internal pull- up resistor. table 5: main clock interface (phy) 88E8053 pin # pin name pin type description 15 xtali i input from 25 mhz crystal or oscillator. 14 xtalo o output to 25 mhz crystal. marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 12 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table 6: analog (phy) 88E8053 pin # pin name pin type description 10 lom_ disablen i used in lom applications. the lom_disablen pin is active low 0 = lan on motherboard (lom) disabled 1 = lom enabled 12 vaux_avlbl i vaux available signal. 11 switch_vcc o switch to vcc. 47 vmain_avlbl i vmain available signal. 9 switch_vaux o switch to vaux. 24 25 hsdacp hsdacn analog o, d phy test pin. these pins are used for debug only. if debug is not important and there are board space constraints, these pins should be left floating. 16 rset analog i phy constant voltage reference. external 5.0 k ? 1% resistor con- nection to vss. 4 ctrl25 o analog regulator control. this signal controls an external pnp transistor to generate the 2.5v power supply. 3 ctrl12 o analog regulator control. this signal controls an external pnp transistor to generate the 1.2v power supply. table 7: led interface 88E8053 pin # pin name pin type description 59 led_actn ttl, d parallel led activity indicator. active low. 60 led_ link10/100n ttl, d parallel led output for 100base-t link or speed. if the led_link10/100 pin is active, it indicates 100 mbps. active low. 62 led_link1000n ttl, d parallel led output for 1000base-t link. active low. 63 led_linkn ttl, d parallel led output for 10/100/1000base-t link. active low. table 8: test pins 88E8053 pin # pin name pin type description 46 testmode i, pd selection of internal test. (default pull-down.) 29 tstpt o analog test point. marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 13 signal description pin description table 9: power & ground 88E8053 pin # pin name pin type description 64 vdd25 power power to ttl i/os. 2.5v 19 22 28 32 51 52 57 avddl power analog power. 2.5v - copper 23 avdd power analog power. 2.5v (for 3gios) 1 8 40 45 61 vddo_ttl power power to ttl i/os. 3.3v (pin 8 can be used as power to vaux 3.3v - see application note for details.) 2 7 13 33 39 44 48 58 vdd vdd power. 1.2v 0 epad ground ground. table 10: no connect 88E8053 pin # pin name pin type description 42 43 nc -- no connect. these pins must be left floating. marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 14 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications section 2. functional description 2.1 overview this single link gigabit ethernet c ontroller device comes with a pci expr ess interface and gigabit ethernet ca- ble connectivity. the device integrates pci express in terface, bmus, ram, mac, phy, and serdes cores. an optional 128/256 kbyte spi flash memory holds bootco de and configuration data. the configuration data is read by the spi flash memory loader after power on reset. all writable registers on the pci device, may be reloaded from the spi flash memory. the spi flash memory is required if other rom options are not available for bootcode (pxe). the vpd data are st ored within an onboard twsi eeprom. in absence of this twsi eeprom the vpd data may be stored within the spi flash memory. the pci device is controlled by the system?s cpu through t he pci target interface. the description of all accessi- ble registers is concentr ated in the chapters configuration register file and control register file . most regis- ters are controlled only at initialization time. receive/transmit data and descriptors are transferred to/f rom system memory over the pci interface controlled by the buffer management units (bmu). the ge link ha s a receive queue, and a asynchronous transmit queue. these two queues run independently. the bmu manages the da ta transfer to/from syst em memory. this is con- trolled by the system?s cpu through descriptors allocating memory buffers. descriptors are organized in chained lists. the pci fifo provides data/space for burst transfers. the rambuffer control logic organizes programmable rambuffer areas in the internal sram as fifos for bufferi ng of receive/transmit data (e.g. in order to prevent re- ceive overflows). it controls the dataflow between its pci fifo and mac fifo through the allocated rambuffer. packets may be transferred in flow through mode or store & forward mode. pci accesses are arbitrated in a hierarchical priority sc heme. transfer length is optim ized for cache line sizes and best pci command usage (descriptors and data). the pc i master supports fully misaligned transfers of re- ceive/transmit data (descriptors must be located at dword boundaries). the ram interface arbitrates ram accesses requested by the rambuffer control logics in a rotating priority scheme generally. in some cases the priority scheme is adapted dynamically (e.g. risk of receive overflow, rate control on transmit). re-arbitration takes place on c hunk level. chunk length is programmable, default is 32 qwords. for transmit packets a tcp/ip checksum may be calculat ed and inserted, on receiv e packets, tcp/ip check- sum is calculated. tcp/ip checksum generation/checking is co ntrolled by the descriptors. tcp/udp checksum generation and insertion can be handled also for large fragmented packets. for udp checksum is calculated over all the appropriate packets and is insert ed into the first packet of the sequence. figure 2 shows the device block diagram. marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 15 functional description overview figure 2: block diagram pci express spi twsi eeprom (vpd) te m p . / voltage sensor mdi rj45 magnetics/ pci config. registers status/ control registers irq handling registers phy gmac mdc mdio gmii receive queue mac rx fifo mac tx fifo async. transmit queue link 88E8053 chip twsi twsi ytb ta r g e t master biu status bmu polling unit flash memory spi flash memory loader sram marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 16 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.2 pci-express features table 11 lists the features of the pci-express interface. table 11: general pci-express features feature name description standard compliance ? compliant with pci-express base 1.0a specification . pci-express port ? 2.5 ghz signaling. ? x1 link width. ? width strapped on reset. ? support link reversal and lane polarity reversal. master transaction types ? support of up to 8 outstanding np requests as a master (requester). ? all memory transacti ons, except lock related. target transaction types ? support of 2 outstanding non-posted r equests as a target (completer). ? all memory transacti ons, except lock related. ? i/o transactions - supported only when working in legacy endpoint mode. ? configuration transactions - type0 only. ? support up to 8b target accesses. message support ? interrupt messages. ? error messages. ? pm related. ? hot-plug related. ? not supported - lock related and vendor specific messages. configuration space. ? extended 4 kb pci-express configuration space. ? single function device. ? external configuration register file. interrupts ? support of both msi and interrupt messages. ? external biu master agent is responsible for msi generation. error reporting ? full support of pci-express base-line error reporting. ? full support of advanced error reporting capability. ? three error severity levels: correctable, uncorrectable - non-fatal and uncor- rectable - fatal. ? header logging and pointer to first uncorrectable error. ? programmable error severity. ? pci error mapping - mapping of erro rs to pci error re porting mechanism. address space ? three 64bit memory bars for internal registers access. ? one i/o bar for internal registers access. ? expansion rom bar. virtual channels ? support of baseline tc0-vc0 mapping. ? one virtual channel (vc) hardware resource. marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 17 functional description pci-express features power management ? supported sw directed pm states: l0, l1, l2, l3 ? supported active state link pm states: l0s-rx. ? support of wake event generation from all device pm states including d3 hot . ? wake event signalling by wake# signal mechanisms. table 12: main pci-express parameters. feature name description max payload size ? 128b maximum read request size ? up to 4 kb rcb - read completion boundary parameter. ? 128b table 11: general pci-express features feature name description marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 18 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.3 spi flash memory the spi flash memory has a size of 128/256 kbyte. for future applications spi flash memories up to 1 mbyte can be handled. figure 3: address space organization of spi flash memory the spi flash memory may be mapped into the memory address space with sizes of 16 kb, 32 kb, 64 kb or 128 kb. the page size is defined by pagesize<1:0> ( our register 1 ). plug-in-go configuration normal operation configuration 0x00000 0x1efff 0x1f000 0x1f7ff 0x1f800 0x1ffff 112kb 2kb 256 2kb vpd 0x1bfff 0x1c000 0x1c0ff 0x1c100 0x20000 0x3ffff 128kb controller code marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 19 functional description spi flash memory if en eprom ( our register 1 ) is not set, the expansion rom base address register is not presented to the configuration register file , the spi flash memory is not mapped to the memory address space. the mapped page is selected by setting page reg<2:0> ( our register 1 ). the base address is defined in the expansion rom base address register . the expansion rom base ad- dress register also holds the page size and romen which controls enabling of the expansion rom. the 4 kbytes sector (0x1f000 - 0x1ffff) holds data configuring the ne twork adapter after perstn . in absence of the twsi eeprom t he spi flash memory contains also vpd data (0x1c000, 0x1c0ff, spi flash memory vpd configuration register ). memory accesses to the spi flash memory are read only. write operations are completed normally on the bus and the data is discarded. for programming of the spi flash memory no additiona l 12v power supply and switching of the programming voltage is required. the spi flash memory (256 kb) is organized in eight sectors with 32 kbytes each and 128 pages (page = 256 byte) per sector: table 13: eight spi flash memory sectors sector address sector 000000 to 007fff 1 008000 to 00ffff 2 010000 to 017fff 3 018000 to 01ffff 4 020000 to 027fff 5 028000 to 02ffff 6 030000 to 037fff 7 038000 to 03ffff 8 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 20 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.4 spi flash memory loader the spi flash memory loader s upports the following features: ? loading of data after perstn from the spi flash memory into the configuration and control register file (where needed). ? the loader is capable of accessing potentially all registers in the control register file space. ? register address and data are stored in 8-byte entries in the spi flash memory. ? the registers may be written with dword, word or byte accesses. ? the 8-byte entries are located on 8-byte boundaries starting at address 0x1f800 (or 0x1f000 for plug-in- go, configurable within spi flash memory loader control register ) of the spi flash memory in increas- ing order. each entry is marked with a key. the selection of plug-in-go or normal operation conf iguration is done depending on the detected power supply by v aux or pci power line. ? if started, the loader reads subsequent ent ries starting with the initial value of the normal loader start address (bit 27:16 in spi flash memory loader configuration register ) or, if plug in go, with the value of the pig loader start address (bit 11:0). ? loading is started by deassertion of perstn or the setting of the spi loader start bit in the spi flash memory control register . ? while loading, accesses to any resource of the netwo rk adapter are terminated by target retry cycles. ? the transferred data after perstn in this way is limited to fulfill the requirements of pci bus 1 . ? the command spi loader start is intended for testing purposes only. it is not recommended to reload the configuration register file by using this command. table 14: first 8 byte unit within normal operat ion configuration region of spi flash memory ? loading boot-code: the boot data can be accessed as byte, word, or dword at a time. all combinations of byte-enables of the pci specification are supported. there is a cache, which holds 2 consecutiv e dwords (8 bytes) of data. initially, there is no valid data in the cache. when a boot access is initiated, consecutive dwords are fetched, starting with the dword containing the requested data. the req uested byte/word/dword is forwarded as soon as the dword that contains the accessed address is loaded. th e loader doesn?t wait for the following dword fetch also to complete. a cache location (dword) is released (decla red empty) when byte 4 in that dword is read out. reading byte 4 may be done by dword/word/byte access. the spi read continues as long as there is at least one empty location in the cache. this means that, in theory, the spi memory could be transferred within one single burst throughout a sequential data load. the burst is broken when there is a jump in address or the access over the pci bus takes too long time and the cache fills up. when requested data is in the cache (hit), data is supplied from the cache and no new spi access is required. a new spi access is initiated when there is a miss (requested data is not found in the cache or that dword is currently being fetched). the cache con- tents are made invalid when the spi memory is written to. ? loading vpd-data: if the vpd-data is in the spi flash memory the whol e 256 byte can be accessed by 8 read-cycles to the vpd area (0x1c000 - 0x1c0ff). the data are stored in the lower dword of the cache. 1. t rhfa perstn high to first configuration access is limited to 2 25 clock cycles. pci express: 1s -> max. 2.8 kb 31:24 23:16 15:8 7:0 address address/upper address/lower reserved be<3:0> key = 0x55 0x1f800 data<3> data<2> data<1> data<0> 0x1f804 marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 21 functional description spi flash memory loader ? programming interface: the data can be written byte, word or dword at a time. all combinations of byte-en ables of the pci specifica- tion are supported. the starting byte could be anywh ere within a page. when the end of the page is reached, the address wraps around to the b eginning of the same page and the da ta will be stored there. this means that the software is capable to handle the se ctor and page borders that no data are lost. note: the same byte can?t be reprogrammed without erasing the whole sector first. ? support of spi flash memories of different vendors: the current spi flash memory devices of different ve ndors vary in their instruction-codes for the read id instruction. after reset the used spi flash memory needs to be identifi ed by the spi flash memory loader. the identification of the flash on the board after perstn should look like this: ? after the release of perstn the spi flash memory loader starts dire ctly to read the configuration data. if the spi flash memory is programmed the loader reads all data into the register-file until key (0x55) can- not be found anymore. then and also if the spi fl ash memory was not programmed at all the loader moves to an idle state to wait for new commands. ? afterwards the software identifies the flash. theref ore the vendor- and device-id are read out of the spi flash memory and the memory type is stored in the rd id protocol bit in spi flash memory control register . depending on the eprom type the software uses different instruction code sets ( spi flash memory opcode 1 and 2 register ). even during identification of the spi flash memory there are two possible protocols to be used. maybe both protocols must be tried by software to read out the spi flash memory id. ? sector erase: due to the fact that the flash is divi ded into sectors only, a write to the vpd or configuration region leads to the erasure and rewriting of the whole vpd/configuration information. reprogrammable vpd during operation of the device can be achieved by the use of an additional twsi eeprom (see chapter 2.5 twsi eeprom on page 22). ? supported instructions for the spi flash memory: ? write - program data into memory array ? chip erase - erase all sectors in memory array ? sector erase - erase one sector in memory array ? wren - set write enable latch - has to be se t before program, chip- and sector-erase ? read - read data from memory array ? rdsr - read status register ? rdid - read vendor and device id (two different protocols) ? nop - no operation marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 22 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.5 twsi eeprom the twsi eeprom is an external memory device for vpd (vital product data). its address space is divided into two parts (see figure 4). figure 4: internal stru cture of twsi eeprom. within the lower address region (0 to 255) the vpd is loca ted. this part contains the read only and writable sec- tion of vpd separated by vpd threshold (see vpd write thr in our register 2 in chapter 3.2.4.1 our register 1 and our register 2 on page 69). in higher addresses the configuration data is stored wh ich is loaded automatically into the asic after perstn with its internal twsi eeprom loader (see chapter 2.6 twsi eeprom loader on page 23). two different configurations may be loaded by t he twsi eeprom loader depending on the current operation mode ?normal? or ?plug in go?. normally this feature is not used due to the existence of the spi flash memo ry, which also holds configuration da- ta. the twsi eeprom is read and written to vi a twsi bus. its twsi address is 0b101000. the size of the twsi eeprom, the amou nt of writable vpd area and the de vice select byte used for vpd twsi accesses are determined by the read only fields vpd rom size , vpd write threshold and vpd devsel 1 in our register 2 (see chapter 3.2.4.1 our register 1 and our register 2 on page 69). these fields can be reloaded from the spi flash memory, if another device is used. for manufacturing programmi ng of the read only part of the twsi eeprom, testmode ( en config write ) must be set. then the whole twsi eeprom is writable. pr ogramming of the twsi eeprom is managed with asic in- ternal registers vpd address and vpd data (see chapter 3.2.4.10 vpd address register on page 78 and chapter 3.2.4.11 vpd data register on page 78). after the next power cycle the read only areas wit hin the twsi eeprom are write protected again 1. hint: vpd devsel must not be overwritten via twsi eeprom in absence of the spi flash memory . this may lead to a complete damage of the board (twsi eeprom must be changed afterwards!!! 0 255 127 256 max. 2 kbyte address vpd read only vpd writable normal configuration data (read only) organized in 8 byte blocks vpd threshold = 1 configuration vpd 511 512 pig configuration data (read only) organized in 8 byte blocks 128 marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 23 functional description twsi eeprom loader 2.6 twsi eeprom loader the twsi eeprom loader looks for configuration data within the external twsi eeprom, although the config- uration data is stored within the spi flash memory and therefore no data is to be read out normally. ? the twsi eeprom loader is active once after the exec ution of the spi flash memory loader (after per- stn). ? it works analogously to the spi flash memory loader and loads startup data into the configuration and con- trol register file (where needed): ? the loader is capable of accessing potentially all registers in the control register file space. ? register address and data are stored in 8-byte ent ries in the twsi eeprom (see table 15 for details). ? the 8-byte entries are located on 8-byte bound aries up from address 256 of the twsi eeprom in increasing order. each entry is marked with a key byte (0x55). ? the asic internal registers may be written with dword, word or byte accesses. ? if started, the loader reads subsequent entr ies starting with the initial value of the twsi eeprom address counter (see 3.2.4.12 twsi eeprom control register on page 79) as long as a valid key is found. ? loading is started by finishing the spi flash memory loader state machine or by setting the flag to start the twsi eeprom loader (see 3.2.4.12 twsi eeprom control register on page 79). ? loading the twsi eeprom via flag in the twsi eeprom control register is intended for testing pur- poses only. it is not recommended to reload the configuration register file using this command. ? while loading, accesses to any resource of the netw ork adapter are terminated by target retry cycles. ? the transferred data after perstn in this way is limited to fulfill the requirements of pci bus 1 . ? this time consuming reading via twsi bus may be deactivated by setting the flag bit to stop (0) in the twsi eeprom control register see 3.2.4.12 twsi eeprom control register on page 79. then the state machine does not even start reading values. ? transformation of the twsi eeprom da ta (8 bytes) into multiple byte/dwo rd memory read accesses from the bus. ? 32-bit read data is received via twsi-bus within one read access. two read accesses are necessary to receive the full information for writing one internal register. ? programming the twsi eeprom is described in chapter 2.5 twsi eeprom on page 22 table 15: data format of first 8 byte block within twsi eeprom twsi access cycle number twsi eeprom address contents 2 0x107 data<3> 0x106 data<2> 0x105 data<1> 0x104 data<0> 1 0x103 address/upper 0x102 address/lower 0x101 reserved be<0:3> 0x100 key = 0x55 1. t rhfa perstn high to first configuration access is limited to 2 25 clock cycles. pci express: 1s -> max. 2.8 kb marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 24 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.7 plug in go unit the plug in go unit decides wether to load normal c onfiguration or pig configuration by the spi flash memory loader. which configuration to select is dependent on the available voltages v main and v aux and if the device is in the d3 state. the plug in go configuration is loaded by the spi flash memory loader when v main is no longer available but v aux and the device is not in d3 state. after a power on (both voltages not availabl e) pig configuration is loaded when only v aux available. else normal configuration is loaded by the spi flash memory loader. see figure below for the complete state description of the plug in go unit: figure 5: plug in go unit state diagram idle pig_mode = 1 loader_start = 0 pig mode pig_mode = 1 loader_start = 1 vmain pig_mode = 0 loader_start = 1 vaux4wol pig_mode = 0 loader_start = 0 !vmain & !vaux !vmain &vaux & d3 vmain vmain !vmain & !vaux vaux & !vmain vmain !vmain & vaux & !d3 loader_start = 1 causes the spi flash memory loader to load the configuration once after entering the state pig_mode = 0: normal configuration is loaded by the spi flash memory loader pig_mode = 1: plug in go configuration is loaded by the spi flash memory loader marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 25 functional description interrupts 2.8 interrupts chip internal interrupt handling is done with the following internal signals: ? irq is asserted when at least one of the unma sked interrupt sources is active (interrupt). when irq is not asserted, then none of the unmasked interrupt sources is active or internal in terrupt masking line isr_mask is active. ? isr_status is asserted (set to ?1?) when entering th e interrupt service routine: ?isr mode?. isr_status is deasserted (set to ?0?) when leaving the interrupt service r outine: ?normal mode?. ? isr_mask shows if currently all interr upts are masked (regardless of inte rrupt mask register settings). the two internal signals irq and isr_status show the current state of interrupt processing: isr_status is used by the status bmu to accelerate the proce ssing according to the threshold settings for the sta- tus fifo during interrupt processing. the interrupt sour ce register holds the interrupts of all resources (see chapter 3.3.2.4 interrupt source reg- ister on page 130). each interrupt is maskable by the interrupt mask register (see chapter 3.3.2.5 interrupt mask register on page 131). all unmasked interrupts are or?ed and propagated to the internal interrupt line irq . interrupts generated by hardware checks are readable via the interrupt hardware error source register (see chapter 3.3.2.6 interrupt hw error source register on page 131). each interrupt is maskable by the interrupt hardware error mask register (see chapter 3.3.2.7 interrupt hw error mask register on page 132). all un- masked interrupts are or?ed and propagated to the interrupt source register as interrupt hardware error. the interrupts from the mac are readable from the mac interrupt source registers (see chapter 3.3.2.54 mac interrupt source register on page 201) . each interrupt is maskable by the mac interrupt mask registers (see chapter 3.3.2.55 mac interrupt mask register on page 202). all unmasked interrupts are or?ed and prop- agated to the interrupt source register as mac interrupt. an interrupt from a masked source can still be read from its source register . an interrupt is cleared and/or disabled as stated in the description of the related interrupt resource. the special interrupt source registers mirror the interrupt source register with special functionality adapted to typical sw handling: table 16: interrupt processing signals irq isr_status interrupt state comment 0 0 idle no interrupt request is pending 1 0 request interrupt pending, but not yet in process 0 1 processing interrupt is served but not yet fin- ished. all further interrupts masked marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 26 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications ? special interrupt source register 1: if the internal interrupt line irq is asserted, the read value is the same as in the interrupt source register . if the internal interrupt line irq is not asserted, the read value is 0. if the internal interrupt line irq is asserted, reading the special interrupt source register 1 masks all inter- rupts. as a result the internal interrupt line irq is deasserted. ? special interrupt source register 2: if the internal interrupt line irq is asserted, the read value is the same as in the interrupt source register . if the internal interrupt line irq is not asserted, the read value is 0. if the internal interrupt line irq is asserted, reading the special interrupt source register 2 masks all inter- rupts and sets isr_status flag to ?isr mode?. as a re sult the internal interrupt line irq is deasserted. ? special interrupt source register 3: if the internal interrupt line irq is asserted, the read value is the same as in the interrupt source register . if the internal interrupt line irq is not asserted, the read value is 0. reading the special interrupt source register 3 always masks all interrupts. as a re sult the internal inter- rupt line irq is deasserted. if the internal interrupt line irq is asserted, isr_status flag is set to ?isr mode?. all interrupts can be moderated by the irq moderation timer . moderation is controllable individually for each interrupt by the interrupt moderation mask registers. there are two modes of signaling interrupts (internal interrupt line irq is active) to the host system: ? via interrupt line intan: the internal signal irq is forwarded to the pci signal inta# (unless inhibited by regis- ter setting). table 17: effects on reading the special interrupt source registers special interrupt source register 1 special interrupt source register 2 special interrupt source register 3 read value when irq asserted interrupt source register interrupt source register interrupt source register read value when irq not asserted 0 0 0 isr_status set to ?isr mode? - when irq is asserted when irq is asserted masking of all interrupts only, when irq is as- serted only, when irq is as- serted always internal irq line deasserted after- wards deasserted after- wards deasserted after- wards marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 27 functional description interrupts ? via msi (message si gnaled interrupt): the msi agent notifies the interrupt via busmaster write to the defined host memory address. when leaving the isr and all interrupt sources have been cleared, the msi agent is in state idle and waits for new interrupts. if there are still active interrupt s ources or a new interrupt source is set to active, irq is asserted again and the msi agent is triggered for a new interrupt request. the mode is selected with msi enable bit in msi message control register. 2.8.1 irq moderation timer the irq moderation timer (see chapter 3.3.2.29 irq moderation timer registers on page 147) is a program- mable 32-bit downcounter with a resolution of one core clock cycle (6.4 ns, t max = 21.47 s) for the usage as time- base for irq moderation. the command interrupt moderation timer start loads interrupt mode ration timer with interrupt moderation timer init value and starts counting down. reaching zero or loaded with zero the interrupt mode ration timer is reloaded with interrupt moderation timer init value . the interrupt moderation timer controls the assertion of the internal interrupt line irq by gating the interrupts as defined by the interrupt moderation mask registers . if the interrupt moderation timer is stopped or reaches zero, the gate opens and allows the masked interrup ts to propagate to the bus. the assertion of irq has been caused by one of the masked interrupts, th erefore delayed until the next time, the interrupt moderation timer reaches zero. irq is kept asserted until the appr opriate operation of clearing the interrupt request is completed. the deassertion of irq is not affected. the interrupt moderation timer may be stopped by the command interrupt moderation timer stop . while hw reset or sw reset the interrupt mode ration timer is stopped and the gate is closed. after releasing sw reset the gate is initially open until the interrupt moderation timer is loaded with a value other than zero and started. marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 28 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.8.2 message signaled interrupts (msi) reporting interrupts to the host system via msi is done, when the msi enable bit is set in msi message control register. interrupt line inta# is not used in this mode. this chip is capable of handling one msi message. this is specified also in the msi control register . the location for the msi message is defined in register msi message address upper/lower (64 bit). at this lo- cation within the host memory the interrupt message of the chip is written to. the message itself is stored within register msi message data register . the msi agent detects an active internal interrupt line irq and starts a busmaster write to the defined msi address with the defined msi message data . the host system now detects a msi message at the def ined location and starts an interrupt service routine. during the isr all interrupts are masked. after completion of the isr the interrupts are unmasked again and the irq line is released in case of solving all in- terrupt reasons during the isr. otherwise the interrupt is signaled again to the host. 2.9 buffer management units (bmu) the buffer management units are the interface fo r the bus interface unit (biu) to the queues. the internal requests are presented as one for each queue. guaranteed length of transferable data is derived from the data provided by the bmu and the fifo. the master backends are also providing the multiplexers fo r positioning of data words at the right byte lanes on misaligned transfers and to revert byte ordering for descriptor words depending on rev bytes desc . the position of the multiplexers are controlled by the bmus. 2.9.1 format of descriptor and status list elements communication between host and pci device is done via in terchanged list elements prov ided by the host within its memory space. chip internal descriptors can be modified via list elemen ts and control functions are initiated or status information is reported. all list elements of the different agents are based on the same structure (see figure below): ? width of the list elements is always 64 bit ? bit 63 is the own bit: it marks the ownership of the list element: 1: the pci device is owner of the list element 0: the host is owner of the list element ? the following 7 bits (bit 62... bit 56) contain the opcode for this list element. the opcode defines the meaning of the remaining fields of the list element. the different opcodes ar e assigned to the different tasks as follows: marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 29 functional description buffer management units (bmu) ? the control field (bit 55.. bit 48) specifie s additional attributes of the list element ? the remaining 48 bits (bit 47.. bit 0) hold data according to the opcode and control information. figure 6: base format of the list elements the list elements of each task group are described in detail within the according chapters. table 18: opcode assignments opcode (hex) task group 0x00 - 0x0f not defined 0x10 - 0x1f tcp sum parameter or function 0x20 - 0x2f register updates for rx and tx 0x30 - 0x3f not defined 0x40 - 0x4f dma for rx and tx 0x50 - 0x5f not defined 0x60 - 0x6f status list functions 0x70 - 0x7f special actions (e.g. put index) o w n opcode control data data data data data data 63 62 56 55 48 47 0 31 32 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 30 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.9.1.1 receive descript or list element figure 7 shows all different list elements processable by the rx bmu. figure 7: rx descriptor list element definition o w n opcode control buffer length buffer address low dword 63 62 56 55 48 47 0 31 32 packet o w n opcode control buffer length buffer address low dword 63 62 56 55 48 47 0 31 32 buffer o w n opcode reserved reserved buffer address high dword 63 62 56 55 48 47 0 31 32 addr64 o w n opcode reserved reserved tcp start sum 1 63 62 56 55 48 47 0 31 32 tcppar tcp start sum 2 marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 31 functional description buffer management units (bmu) the following opcodes are valid for rx descriptor list elements: the own bit signals the ownership of the list element: ? own = 1: the pci device is owner of the list element ? own = 0: if own = 0 in a list element detected by the bmu, it stops processing list elements and asserts an interrupt request irq. the control field defines attributes to the descriptor: table 19: rx descriptor li st element valid opcodes opcode (hex) 7 bit opcode name description of assigned list element 0x12 tcppar bits 31:0: tcp sum start address 1 and 2 0x21 addr64 bits 31:0: new value for the buffer address high regis- ter of the rx bmu 0x40 buffer follow up buffer for a packet bits 55:48: buffer control bits bits 47:32: buffer length bits 31:0: buffer address low one buffer list element must be skipped on the start of a new packet. it enables a dma request by the rx bmu to write receive data. 0x41 packet first buffer of a packet bits 55:48: buffer control bits bits 47:32: buffer length bits 31:0: buffer address low a packet list element enables a dma request by the rx bmu to write receive data. other not supported by rx bmu processing of list elements is stopped and an interrupt irq is asserted by bmu. table 20: control field definitions bit # control bit meaning (when set to 1) 7 reserved 6 frc_stat list element forces a burst of the status fifo 5:2 reserved 1 calsum calculate checksum for this packet 0 reserved marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 32 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.9.1.2 transmit descriptor list element figure 8 shows all different list elements processable by the tx bmu. if not mentioned explic itly the ordering is lit- tle endian. figure 8: tx descriptor list element definition o w n opcode control buffer length buffer address low dword 63 62 56 55 48 47 0 31 32 packet o w n opcode control buffer length buffer address low dword 63 62 56 55 48 47 0 31 32 buffer o w n opcode reserved reserved buffer address high dword 63 62 56 55 48 47 0 31 32 addr64 o w n opcode control buffer length buffer address low dword 63 62 56 55 48 47 0 31 32 large send o w n opcode reserved vlan reserved 63 62 56 55 48 47 0 31 32 vlan o w n opcode reserved buffer address high dword 63 62 56 55 48 47 0 31 32 addr64 + vlan o w n opcode reserved reserved reserved 63 62 56 55 48 47 0 31 32 lrglen large send length o w n opcode reserved reserved 63 62 56 55 48 47 0 31 32 lrglen large send o w n opcode lock number tcp sum init value tcp sum start 63 62 56 55 48 47 0 31 32 tcp lisw* tcp sum write + vlan segment length *l, i, s, w stand for the fields. not all are used. (big endian) vlan (big endian) vlan (big endian) (big endian) marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 33 functional description buffer management units (bmu) the following opcodes are valid for tx descriptor list elements: table 21: valid opcodes for tx descriptor list elements opcode (hex) 7 bit opcode name description of assigned list element 0x12 tcp __s_ load value from list element: bits 31:16: tcp sum start address 0x16 tcp _is_ load value from list element: bits 47:32: tcp sum init value bits 31:16: tcp sum start address the byte order within the tcp sum init value is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). 0x18 tcp l___ bits 55:48: lock this number of packets set tcp lock for number of packets. 0x19 tcp l__w bits 55:48: lock this number of packets load value from list element: bits 15:0: tcp sum write address write tcp sum into this packet. 0x1b tcp l_sw bits 55:48: lock this number of packets load values from list element: bits 31:16: tcp sum start address bits 15:0: tcp sum write address write tcp sum into this packet. 0x1f tcp lisw bits 55:48: lock this number of packets. load values from list element: bits 47:32: tcp sum init value bits 31:16: tcp sum start address bits 15:0: tcp sum write address write tcp sum into this packet. there are several tcp parameter opcodes, but not all combinations are valid. valid combinations: tcp lisw, tcp l_sw, tcp l__w, tcp l___, tcp _is_, tcp __s_. the byte order within the tcp sum init value is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). 0x21 addr64 bits 31:0: new value for the buffer address high regis- ter of the tx bmu marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 34 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 0x22 vlan bits 47:32: new value for vlan tag register of the tx bmu the byte order within the vlan tag value is big endian: the msb is in the lower byte (bit 39:32) and the lsb is in the higher byte (bit 47:40). 0x23 addr64 + vlan bits 47:32: new value for vlan tag register of the tx bmu bits 31:0: new value for the buffer address high regis- ter of the tx bmu the byte order within the vlan tag value is big endian: the msb is in the lower byte (bit 39:32) and the lsb is in the higher byte (bit 47:40). 0x24 lrglen bits 15:0: mtu for tcp segmentation 0x26 lrglen + vlan bits 47:32: new value for vlan tag register of the tx bmu bits 15:0: mtu for tcp segmentation the byte order within the vlan tag value is big endian: the msb is in the lower byte (bit 39:32) and the lsb is in the higher byte (bit 47:40). 0x40 buffer follow up buffer for a large send or normal packet bits 55:48: buffer control bits bits 47:32: buffer length bits 31:0: buffer address low it triggers a dma request by the tx bmu to read transmit data. 0x41 packet first buffer of a normal packet: bits 55:48: buffer control bits bits 47:32: buffer length bits 31:0: buffer address low a packet list element enables a dma request by the tx bmu to read transmit data. 0x43 large send first buffer of a large send packet: bits 55:48: buffer control bits bits 47:32: buffer length bits 31:0: buffer address low a packet list element enables a dma request by the tx bmu to read transmit data. other not supported by tx bmu processing of list elements is stopped and an interrupt irq is asserted by bmu. table 21: valid opcodes for tx descriptor list elements opcode (hex) 7 bit opcode name description of assigned list element marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 35 functional description buffer management units (bmu) the own bit signals the ownership of the list element: ? own = 1: the pci device is owner of the list element ? own = 0: if own = 0 of a list element detected by the bmu, it stops processing list elements and asserts an interrupt request irq. the control field defines attributes to the descriptor: table 22: control field definition attributes to the descriptor bit # control bit meaning (when set to 1) 7eop descriptor is last one of a packet 6 frc_stat descriptor forces a tx stat us element in the status fifo 5ins_vlan insertion of vlan tag from tx vlan tag register into packet 4 locksum start of lock packet sequence (number of packets stored in lock register). to be set only for the first packet of a lock se- quence to accept value from internal lock register (lock number value transmitted with last tcp_lisw list element). the number of locked packets is put in the ram- buffer subsequently. 3initsum start checksum calculation new for this packet and use value of init register for initialization of check- sum calculation. 2 writesum write checksum value to th is packet at write posi- tion. 1 calsum calculate checksum for this packet 0 udptcp 1: calculate udp checksum for this packet 0: calculate tcp checksum for this packet marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 36 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.9.1.3 status list element figure 9 shows all different list elem ents processable by the status bmu. figure 9: status list element definition o w n opcode link rx frame length rx frame status word 63 62 56 55 48 47 0 31 32 rx o w n opcode link (vlan tag) rx frame timestamp 63 62 56 55 48 47 0 31 32 rx time- o w n opcode link vlan tag reserved 63 62 56 55 48 47 0 31 32 rx vlan status stamp o w n opcode reserved txs2 done 63 62 56 55 48 47 0 31 32 tx txa2 done txs1 done txa1 done index o w n opcode link (vlan tag) tcp sum 2 63 62 56 55 48 47 0 31 32 tcp sum tcp sum 1 (+vlan) o w n opcode link reserved rss hash value 63 62 56 55 48 47 0 31 32 rss hash little endian little endian big endian little endian big endian big endian big endian big endian little endian t c p i p marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 37 functional description buffer management units (bmu) the following opcodes are valid for status list elements: table 23: valid opcodes for status list elements opcode (hex) 7 bit opcode name description of assigned list element 0x60 rx status generated by the rx bmu for each packet: bits 55:48: link number bits 47:32: rx frame length bits 31:0: rx status word 0x61 rx timestamp generated by the rx bmu for each non-vlan packet, if the timestamp timer is enabled and rss disabled 1 : bits 55:48: link number bits 31:0: rx timestamp 0x62 rx vlan generated by the rx bmu for each vlan packet and the timestamp timer and check summing is disabled: bits 55:48: link number bits 47:32: vlan tag the byte order within the vlan tag value is big endian: the msb is in the lower byte (bit 39:32) and the lsb is in the higher byte (bit 47:40). 0x63 rx timestamp + rx vlan generated by the rx bmu for each vlan packet and the timestamp timer is enabled and rss is disabled: bits 55:48: link number bits 47:32: vlan tag bits 31:0: rx timestamp the byte order within the vlan tag value is big endian: the msb is in the lower byte (bit 39:32) and the lsb is in the higher byte (bit 47:40). 0x64 tcp sum generated by the rx bmu for each non vlan packet, if checksumming is enabled bits 55:48: link number bits 31:16: tcp sum 2 bits 15:0: tcp sum 1 the byte order within the tcp sum is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). 0x65 rx rss hash generated by the rx bmu for each packet, if rss hash calculation is enabled) bits 55:48: link number bit 33: tcp flag bit 32: ip flag bits 31:0: rss hash value marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 38 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.9.1.4 special action list elements figure 10 shows all different special action list elements. figure 10: special action list elements 0x66 tcp sum + vlan generated by the rx bm u for each vlan packet, if check- summing is enabled bits 55:48: link number bits 47:32: vlan tag bits 31:16: tcp sum 2 bits 15:0: tcp sum 1 the byte order within the tcp sum is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). the byte order within the vlan tag value is big endian: the msb is in the lower byte (bit 39:32) and the lsb is in the higher byte (bit 47:40). 0x68 tx index if an status burst is scheduled and at least one of the tx done indices differs from its tx report index, a tx index le is appended as last le in the status burst. bits 31:25: txs2 done index bits 24:16: txa2 done index bits 15:8: txs1 done index bits 7:0: txa1 done index other not supported by status bmu 1. note, that rx rss hash le and timestamp le can only be generated exclu- sively. as long as the rss hash feature is enabled, no timestamp le is gener- ated. table 23: valid opcodes for status list elements opcode (hex) 7 bit opcode name description of assigned list element o w n opcode link res. 63 62 56 55 48 47 0 31 put index 32 16 15 12 11 rx put index txa put index res. res. 44 43 27 28 res. marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 39 functional description buffer management units (bmu) the following opcodes are valid for special action list elements: 2.9.2 tcp/udp processing of rx and tx bmu tcp checksum may be calculated by rx and tx bmu for the processed packet. 2.9.2.1 tcp checksum in rx direction in rx direction two tcp c hecksums may be calculated from two differ ent configurable start positions (refer to 3.3.2.41 bmu registers for receive queues on page 158 and 2.9.1.1 receive descriptor list element on page 30). 2.9.2.2 tcp/udp checksum for si ngle packets in tx direction in tx direction tcp or ud p checksum may be calculated. the control bit udptcp must be set accordingly. init va lue, start address and write address are defined for the tcp/udp sum. store and forward (st&fwd) and calculat e tcp/udp sum for this buffer/packet must be set. 2.9.2.3 udp checksum for fragment ed packets in tx direction when large udp packets are split into several smaller packets. udp checksu m is calculated for the original large packet. therefore the udp is calculated over the data ar eas of several small packets and the resulting checksum is inserted within the udp header field of the first packet. the address for the insertion of the checksum is loaded explicitly and is not updated autom atically by a new packet start. table 24: valid opcodes for special action list elements opcode (hex) 7 bit opcode name description of assigned list element 0x70 put index list element for hardware polling unit: bits 55:48: link number bits 47:44: reserved bits 43:32: rx put index bits 31:28: reserved bits 27:16: txs put index bits 15:12: reserved bits 11:0: txa put index other not defined yet marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 40 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications figure 11: udp checksum across several packages the software can handle the several packets belonging to one udp checksu m processing in two order modes. the packets are handled in the original order to the hardw are or they are transferr ed starting with packet number 2 up to the last of the sequence and terminated by the first one. udp processing for packets in original order (1, 2,..., n): ? set tcp lock for n packets, which inhibits transmission of the next n packets coming in. ? set tcp sum write: remember the ram buff er address, where to write the tcp sum. ? set tcp sum init: initialize the checksum adder with a start value. ? set tcp sum start: set the start address for checksum calculati on for the 1st packet. ? buffer with 1st packet: calculate checksum with current parameters. ? set tcp sum start: set the start address for che cksum calculation for the 2n d and following packets. ? buffer with 2nd and following packets: ca lculate checksum with current parameters. ? eof of last packet clears tcp lock, writes checksum to first packet and allows tr ansmission of all packets. in this case the packets can be sent after the checksum was calcul ated including the last packet. udp processing for packets in ?vendel? order (2,..., n, 1): ? set tcp sum init: init ialize the checksum adder with a start value, when co ntrol bit initsum is set to ?1? for the current packet. ? set tcp sum start: set the start address for che cksum calculation for the 2n d and following packets. ? buffer with 2nd and following packets: ca lculate checksum with current parameters. ? packets are sent immediately after complete reception (2.. n). ? set tcp sum write: remember the ram buffer address, where to write the tcp su m. for the last transmitted packet (number 1) the control bit writesum must be set to ?1?. ? set tcp sum start: set the start address for checksum calculati on for the 1st packet. ? buffer with 1st packet: calculate checksum with current parameters. ? eof of packet 1 clears tcp lock, writes checksu m to packet 1 and allows transmission of packet 1. in the ?vendel? case the packets can be sent just after receipt and the calculated checksum is inserted in packet 1, which is received and transmitted last. 2.9.3 prefetch unit each rx or tx fifo has its own prefetch fifo. this block occurs two times per link: ? rx prefetch unit ? tx prefetch unit mac header ip header udp header data mac header ip header udp header data mac header ip header data data mac header ip header 1 2 3 marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 41 functional description buffer management units (bmu) the prefetch unit does intelligent prefetching of list elements for a bmu. the host software may update the according put index register continuously to trigger t he prefetch of new list el- ements completely automatically. alternatively the put index value is po lled continuously by the hw polling unit out of a software defined memory location and the put index register of the pr efetch unit is updated by the hw polling unit. a prefetch of new list elements is st arted whenever put index register differ s from get index register and there is at least the minimum free space left in the prefetch fifo. the number of new list elements which are to be prefetched is calculat ed (put index - get index and minimu m free space of prefetch fifo). the prefetch fifo is written by the biu and read by the bmu. it works fully synchronously to the biu ma ster interface and the associated bmu. it is controlled by the following parameters and variables: 2.9.4 status bmu the status bmu handles information flow between hardware and host software. this is done with a status list area within the host memory space. this ar ea is provided by the software and must be large enough for the reception of status information about a number of packets for the two receive and transmit table 25: prefetch control parameter and variables name description list start address low & high 64 bit pointer to the beginning of the descriptor list within the host buffer. defined by software during queue initialization. list length size of the descriptor list area in bytes. defined by software during queue initialization. get index pointer to the next list el ement, which is to be prefetched. defined by software during queue initialization. updated automatically on each prefetch burst. get length number of list elements which may be prefetched by the next prefetch burst. number = put index - get index limitation: a guaranteed minimum space mu st be left free within the prefetch fifo. put index pointer to the last list element put by host software. either written by host software each time new list elements haven been added to the descriptor list, or automatically updated by a put index poll request in hw polling mode. fifo read pointer read address for fifo memory updated automatically when bmu proc eeds to the next list element. fifo write pointer write address for fifo memory updated automatically on each prefetch burst. related closely to the get index. fifo level fifo filling level. base for trigger condition for polling and prefetch bursts. marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 42 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications queues. there is no hardware mechanism to prevent the st atus bmu from overwriting previous status list ele- ments before they are processed by the host software. the status list is write only for the hardware. the host software resets the own bits of the list elemen ts it has already processed to prevent wrapping around the list. all rx status list elements concerning the same packet ar e kept together. they are put to the list in the following order (ascending opcode): ? rx checksum (+vlan) if checksumming is enabled ? rx vlan, if vlan packet and previous les did not comprise vlan. ? rx status: the list element holding rx status word is always the last within this block. the status bmu is controlled by the following parameters and variables: if one of the tx done conditions is fu lfilled, a tx index list element is appended as last list element in the status burst. table 26: status bmu control parameters and variables name description list start address low & high 64 bit pointer to the beginning of t he descriptor list within the host buffer. defined by software during queue initialization. list length size of the descriptor list area in bytes. defined by software during queue initialization. txa report index last reported tx done index for the transmit queues tx index threshold threshold for initiating a status burst put index pointer to the next free list elem ent in the host memory descriptor list area. if put index and get index are equal no element is in the fifo. fifo read pointer read address for fifo memory updated automatically on each status burst. fifo write pointer write address for fifo memory fifo watermark fifo watermark fo r initiating a status burst. fifo isr watermark fifo wa termark for initiating a status burst during isr. level timer if the status fifo is not empty the level timer is started. when expired a status burst is triggered tx timer the timer is started when the tx d one index differs from its tx request index. when expired a status burst is triggered. isr timer during isr the isr timer is used instead of the level timer. marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 43 functional description buffer management units (bmu) a burst to the status list affects the following registers and timers: ? tx report index = tx done index for the tx queues after the burst to the status list an interrupt status list is asserted. bit status bmu in interrupt source register is asserted. if new list elements reach the status fifo before software star ts interrupt processing, they are queued up in the fifo. as soon as software starts interrupt processing (e.g. clears irq mask register) the status fifo uses other moderation parameters: the level timer is replaced by an isr timer, that is set by software to expire shortly be- fore the expected leaving of the isr (i nterrupt service routine). the watermark is replaced by the isr watermark, which triggers bursts earlier while software is in the is r. this way the status bmu fifo is kept empty and all queued and newly incoming list elements are forwarded to the biu as soon as possible. the tx done index of the tx queue is connected to the status bmu. the status bmu maintains a tx report in- dex for the tx queue holding the last state of the tx done index last reported to the host. a tx index timer is set to its initial value and started ea ch time one of the tx done index differs from its tx re- port index. it is stopped and reset to zero when the tx report index is updated. each time one of the done index differs from its repo rt index and the difference is higher than the tx index threshold or the tx timer expires, a status burst request is asserted to the status bmu. during the processing of a status burst, new list elemen ts may be queued up and they are also sent within an im- mediately following burst (burst size and timer values are lower than for normal burst requests; see figure 12: sta- tus interrupt moderation ). the tx index list element will be appended to the last element of the last status burst. right before being appended the states of the tx done index is sampled and inserted into the tx index list ele- ment and the tx done index is copied to the according tx report index. marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 44 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications figure 12: status interrupt moderation idle request: irq on bus is active process: sw is in interrupt handling routine use normal parameters to queue up status les moderation condition fulfilled, a status burst is initiated use normal parameters to queue up status les sw enters interrupt handler: specific in or out instruction use special parameters to queue up status les sw exits interrupt handler: specific in or out instruction marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 45 functional description buffer management units (bmu) 2.9.5 polling unit the polling unit is used to automatically up date the put index regi sters of the bmus. it runs synchronously to the bi u master interface and all bmus. it is a read only agent on t he biu?s request interface. the put indices and their enable bits for all bmu descriptor lists are stored in a contig uous memory area within the host buffer which is formally organized as two list elements. the polling unit reads always both list elements at once and the values are stored in an internal register bank. if the enable bit of the put index is set, the value is fo rwarded directly to the acco rding bmu without using the tar- get bus. each time the descriptor poll timer expires a poll request is initiated. the descriptor poll timer runs with clk_core to have a fixed timebase. for testing a poll request can be starte d by software via poll control register. the polling unit is controlled by the following parameters and variables: a check interrupt is generated on one of the following reasons: ? the received list element has the own bit (bit 63) not set. ? the received list element has a wrong opcode. ? at least one byte enable is not set for the received list element the interrupt is cleared by software with setting the clear irq bit in the poll control register table 27: polling unit contro l parameters and variables name description poll start address low & high 64 bit pointer to the beginning of the descriptor list within the host buffer. defined by software during polling unit initialization. last index index of the last list element to poll. fixed by hardware to 1. two list elements are read always. poll control control bits for polling unit: reset/enable operational on/off do_poll: command for polling marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 46 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.10 timer the timer is a programmable 32-bit downcounter with a resolution of 8 ns (derived from core clock) for the usage as a fixed timebase. the command timer start loads timer with timer init value and starts counting. reaching zero or loaded with zero the timer generates an interrupt irq timer and is reloaded with timer init value . irq timer is cleared by the command timer clear irq . command timer clear irq overrides a concurrent internal interrupt (guaranteeing irq edges). note in order to prevent irq pulses, command timer clear irq should only be issued, if irq timer is pending or if the timer is stopped. the timer may be stopped by the command timer stop . te stin g: test mode is switched on/off by the command timer test on/off . in test mode, clock pulses may be generated by software command timer step . 2.11 timestamp timer the timestamp timer is a programmable 32-bit up counter with a re solution of 8 ns (derived from core clock) for the usage as a time base for time stamping the receive frames. the command timestamp timer start starts counting (fro m its current value). wrapping from 0xffffffff to zero or loa ded with zero, the timestamp timer generates an interrupt irq times- tamp timer . irq timestamp timer is cleared by the command timestamp timer clear irq . command timestamp timer clear irq overrides a concurrent internal interrupt (guaranteeing irq edges). the timestamp timer may be stopped by the command timestamp timer stop . te stin g: test mode is switched on/off by the command timestamp timer test on/off . in test mode, clock pulses may be generated by software command timestamp timer step . marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 47 functional description wake on lan 2.12 wake on lan via pme line the host system can be woken by the pci dev ice, when a wake up event is detected on the lan in- terface. this may be done for all three operation modes 10/100/1000. the wake on lan feature uses three mechanisms to create a wake up event: ? wake up frame: incoming packets are compared to severa l patterns stored in a ram. a match causes a wake up event. magic packet frame detect: the incoming data stream is searched for a so called ?magic packet frame? that consists of 6 bytes of 0xff followed by 16 iterations of the device?s mac ad dress. if this sequence is found, a wake up event is created. ? link change monitoring: any change of the link status causes a wake up event. 2.12.1 wake up frame logic the wake up frame logic consists of a pattern ram, a re ceive data register, length counters and compare logic for each pattern to compare and a statemachine that pars es the incoming data stream for start and end of packet. a control register holds bits to enable and configure the wake up frame logic and a status register holds bits that show the result of the matching process. the complete set of available registers is described in chapter 3.3.2.57 wake on lan control registers on page 203. the representation of the pattern ram to the software can be found in chapter 3.3.2.58 pattern ram on page 208. the wake up frame logic is run with the mac? s receive clock (same as the mac rx fifo). the pattern ram is a single port sram of 64 words by 128 bits. under wol working condition the ram port is used by the compare logic to read out the patterns for comparison. to access the ram from the pci bus by target read or target write to set up the patterns the wol unit mu st be set to inactive before (bit 1:0 to 0b01 of wol con- trol register). figure 13: organization of pattern ram the pattern ram holds 7 patterns of up to 128 bytes each . each data word consists of two bytes of each pattern on byte 0 .. 6 and byte 8 .. 14, while bit 0..6 of byte 7 an d byte 15 are used as mask bits to enable the comparison of the current byte for each pattern. bit 0 of byte 7 enables the comparison of byte 0 with the current lower byte of the packet, bit 1 enables comparison of byte 1 and so on. byte # /addr. 1514131211109876543210 0x00 mask byte 1 pat 6, byte 1 pat 5, byte 1 pat 4, byte 1 pat 3, byte 1 pat 2, byte 1 pat 1, byte 1 pat 0, byte 1 mask byte 0 pat 6, byte 0 pat 5, byte 0 pat 4, byte 0 pat 3, byte 0 pat 2, byte 0 pat 1, byte 0 pat 0, byte 0 0x01 mask byte 3 pat 6, byte 3 pat 5, byte 3 pat 4, byte 3 pat 3, byte 3 pat 2, byte 3 pat 1, byte 3 pat 0, byte 3 mask byte 2 pat 6, byte 2 pat 5, byte 2 pat 4, byte 2 pat 3, byte 2 pat 2, byte 2 pat 1, byte 2 pat 0, byte 2 ::::::::::::::::: 0x3f mask byte 127 pat 6, byte 127 pat 5, byte 127 pat 4, byte 127 pat 3, byte 127 pat 2, byte 127 pat 1, byte 127 pat 0, byte 127 mask byte 126 pat 6, byte 126 pat 5, byte 126 pat 4, byte 126 pat 3, byte 126 pat 2, byte 126 pat 1, byte 126 pat 0, byte 126 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 48 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications the receive data register clocks in the receive data coming from the mac or the internal loopback path. it is 32 bits wide and samples rx_data each time rx_data_valid is asserted. to serialize the words for comparison with the pattern words a word counter contro ls a word wide multiplexer that puts words 0..1 of the received dword in two consecutive clock cycles to the compare logic. at gigabit speed each 2 clock cycl es a new dword arrives. at 100 mbit and 10 mbit speed each 8 clock cycles a new dword arrives. the word counter starts in the clock cycle after rx_data_valid is asserted with count 0b00 and st ops after 2 clock cycles, if not restarted by another rx_data_valid. the pattern pointer is used as read address at the read only po rt of the pattern ram. it is reset to zero at sop and incremented by two each time the word counter is incremented. the pattern match statemachine contro ls the pattern match operation by initializing the match logic on sop and enabling compare logic between sop and eop. it also contro ls the sampling of the receive data in the receive data register to avoid sampling of the receive status word. the compare logic consists of 7 identical instances of the following components: ? a pattern length register holds the length of the pattern. it is initialized by sw. ? a pattern length counter is loaded at sop from the pa ttern length register and is decremented by two each time the word counter is incremented. as soon as the pa ttern length counter for a pattern reaches zero, it sig- nals the end of the pattern match operation. it can be read and written by sw for test purposes only. ? a word-wide comparator compares the receiv ed word to the current word of the pattern. ? a flip-flop signals matching data. it is set at sop and reset as soon as the comparator signals a mismatch and the pattern mask bit for the current pattern byte is set. also it is reset, if the byte enable for the current byte is not set, but the pattern mask bit is set. if the pattern mask bit for the current byte is not set, the byte is not com- pared, but treated as matching. ? a flip-flop signals the result of the pattern match opera tion. it is reset at sop a nd samples the state of the matching data flag as soon as the complete pattern has been compared. if eop is signaled, before the pattern length counter has expired, this flip-flop remains reset and the pattern does not match. it can be read out in the status register. the control/status register contains the following control bits: ? a radio button to enable/disable the wake up frame logi c. if disabled, all flip-flops, flags and counters of the wake up frame logic are reset to zero. the pattern lengt h registers and the other control bits can be set while the wake up frame logic is disabled. ? a control bit to clear the result status bits for all patterns by sw. ? a control bit for each pattern to enable/disable compar ison of incoming packets with the corresponding pattern. ? a status bit for each pattern to show the result of the last pattern match operation. for writes first the lower three words of the 128 bit pattern word have to be written to the pattern ram data reg- isters, then the upper 32 bits are written to the fourth pa ttern ram data register. in the clock cycle after the fourth pattern ram data register has been wri tten, the complete 128 bit pattern word is written to the according pattern ram location. on reads data is read directly out of the patt ern ram. all four dwords are updated simultaneously. marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 49 functional description wake on lan 2.12.2 magic packet frame detect magic packet frame detect: the incoming data stream is searched for a so called ?magic packet frame? that con- sists of 6 bytes of 0xff followed by 16 iteratio ns of the device?s mac address (see chapter 3.3.2.57 wake on lan control registers on page 203). if this sequence is found, a wake up event is created. note: nevertheless the incoming packet must have a valid destination address or multicast address. 2.12.3 link change monitoring link change monitoring: change of the link status from down to up causes a wake up event. marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 50 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.13 gmac the gigabit ethernet functionality is realized with an integrated gmac module provided by marvell in combination with the phy module. all registers of the gmac are accessible by the cpu and are mapped into the i/o address space gmac regis- ters . the reset line /reset of the gmac is controlled by gmac reset. the gmac runs at core clock (clk_host, 125 mhz). the interfaces to the rx and tx fi fos have their own rx_clk and tx_clk. figure 14: gmac and phy integration mac tx_fifo mac rx_fifo phy data control data control control data data mdi fiber optics magnetics rj45 1.25 ghz serial leds mdc irq stats flow control gmac mdio detect address gmii mac tx mac rx marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 51 functional description phy 2.14 phy the phy module is based on ip (alaska 88e1111 ) provided by marvell. (for detailed information, refer to " 88e1111 integrated 10/100/1000 gigabi t ethernet transceiver", marvell, doc. no. mv-s100649-00). 2.15 leds the 88E8053 device supports 4 led signals. all leds can be driven via register settings . the gphy internal four led lines can be driven in different modes (for detailed information, refer to " 88e1111 integrated 10/100/1000 gigabit ethernet transceiver", marvell, doc. no. mv-s10070 7-00). list of all supported led lines by the 88E8053 device: led_actn, led_link10/100n, led_link1000n, and led_link 2.15.1 led capabilities of 88E8053 all phy controlled leds may also be controll ed directly by soft ware (refer to ? 88e1111 datasheet, integrated 10/ 100/1000 gigabit ethernet transceiver?, marv ell, register 24 and register 25). 2.15.1.1 speed leds the led_link10/100n, led_link1000n, and led_linkn pins are controlled by phy. the led_link10/100 n pin is the parallel led output for 100base- t link or speed. the led_link10/100n pin in- dicates 100 mbps link or speed if active. the led_link1000n pin is the output for 1000base-t link. the led_linkn pin is the parallel output for 10/100/ 1000base-t link. 2.15.1.2 link led the led_link pin is controlled by the phy. (for detailed information refer to the 99e1111 datasheet , integrated 10/100/100 gigabit ethernet transceiver, marvell?, register 24: led control and led interface). marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 52 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 2.16 vpd the network adapter implements vpd as suggested by pci rev. 2.3. it is stored in a twsi eeprom (or in the spi flash memory) and may be accessed through the vpd address register and vpd data register . these registers are mapped writable both in configuration and i/o address space. for detailed description of the twsi eeprom see chapter 2.5 twsi eeprom on page 22. in absence of the twsi eeprom vpd is stored within the spi flash memory. then the vpd cannot be repro- grammed during operation of the device, because rewriting of the spi flash memory is done by sector erase (32 kb). 2.17 twsi interface the twsi interface is controlled either by sw via the interface register or by hw via the twsi control regis- ter and twsi data register . if hw controlled twsi accesses are used, the interface register must be set to in- active values (clock = 1, direction = 0, data = 0). the hw controlled interface can be parameterized in several ways. the size of the target device of the twsi ac- cess (and implicit the number of address bytes/bits to be used) and its devsel byte must be written together with the address to the twsi control register . if the twsi burst bit is set, the twsi inte rface runs 4 byte bursts in page mode, assuming pages of 8 bytes. invalid or erroneous hw controlled twsi accesses that don?t complete, can be stopped by writing a 1 to twsi stop . on completion of a hw controlled twsi access an interrupt irq twsi ready is asserted. 2.18 parity generation/check pci parity checking/generating follows pci specification as even parity on dwords. 2.18.1 internal byte based parity checking/generating byte based parity is generated on data entering the pc i transmit fifos and on data entering the mac receive fifos. for internal status words written to t he ram, parity is generat ed by the ram interface. byte based parity is checked on data leaving the pci receive fifos and on data leaving the mac transmit fifos. parity is also checked on data read from the ram. each parity checker generates an interrupt. all parity interrupts are routed to the interrupt hw error source register . note: even if an interrupt parity error is generated, running operations are continued. parity on the pci bus is generated, check ed and reported following the pci specification. marvell confidential - for dfi only free datasheet http:///
april 20, 2004 copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 53 functional description parity generation/check 2.18.2 parity checking/genera ting on pci as target read data parity is generated for all read accesses to device resources (spi flash memory, asic-registers) in the asic. write data parity is checked for all write accesses to devi ce resources (spi flash memory, asic-registers) in the asic. address parity is checked for all address phases running on the bus. if a write data parity error is detected, parity error is set. status register bit (offset: 0x06, page 60) perr# is as- serted, if parity report response enable is set. if an address parity error is detected, parity error is set. status register bit (offset: 0x06, page 60) serr# is as- serted and signaled error is set, if serr# enable and parity report response enable are set. 2.18.3 parity checking/gener ating on pci as master write data parity is generated for all write accesses to system memory. read data parity is checked for all read accesses from system memory. address parity is generated for al l address phases generated on the bus. if a read data parity error is detected, parity error is set. status register bit (offset: 0x06, page 60) perr# is as- serted and data parity error detected is set, if parity report response enable is set. if perr# is sampled asserted on a write access, parity error is set. data parity error detected is set, if parity report response enable is set. if data parity error detected is set, interrupt irq master error is set. if parity error is set, interrupt irq status is set (see also interrupt register ) . marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 54 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications section 3. register description 3.1 legend throughout this document frame and packet (also stf and stp) are used synonymously. dword stands for double word (4 bytes). qword stands for quadruple word (8 bytes). register descriptions the following conventions are valid for register descriptions: ? write: ? ne = no effect (read only register) ? yes = writable ? sh = special handling as described ? exec = execution of this command, if appropriate bit is set ? ito = writable during initialization and for tests only ? to = writable for tests only ? read: ? aw = as written ? value = as defined by itself ? given number (fixed values typically) commands (single bit) in control registers: the following conventions are valid for commands in control registers: ? commands are executed, if appropriate bit is set ? read value as defined. exclusive commands (xxx start/stop, xxx on/off): the following conventions are valid for exclusive commands: ? commands are executed, if appropriate bit is set to 1. ? setting both commands to 1, has no effect. ? status is readable: 0b01 or 0b10. ? reset value: ? = fixed value or value directly from input pin ? = reset to only by power on and hw reset ? (hw) = reset to only by power on and hw reset ? (sw) = reset to by power on, hw reset and sw reset marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 55 register description pci-express configuration register file reserved registers are still empty within the address space. reserved (legacy) registers are not used within this appl ications but have to be left empty due to former sw com- patibility. 3.2 pci-express configuration register file the configuration register file is mapped into the control register file block 7 (only first 128 bytes) and entirely at blocks 56 up to 60. 3.2.1 overview and address map the table below depicts the layout of the configuration space. byte<3> byte<2> byte<1> byte<0> address header region device id vendor id 0x00 status command 0x04 class code revision id 0x08 bist header type latency timer cache line size 0x0c base address (1 st)/lower 0x10 base address (1st)/upper 0x14 base address (2nd) 0x18 reserved (unused base address) 0x1c reserved (unused base address) 0x20 reserved (unused base address) 0x24 reserved 0x28 subsystem id subsystem vendor id 0x2c expansion rom base address 0x30 reserved new cap ptr 0x34 reserved 0x38 max_lat min_gnt interrupt pin interrupt line 0x3c marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 56 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications device dependent region our register 1 0x40 our register 2 0x44 pm capabilities next item ptr pm cap id 0x48 pm data reg reserved pm control/status 0x4c vpd address register next item ptr vpd cap id 0x50 vpd data register 0x54 twsi eeprom loader control register reserved 0x58 msi message control next item ptr msi cap id 0x5c msi message address (lower) 0x60 msi message address (upper) 0x64 reserved msi message data 0x68 pci-x command register reserved pci-x cap 0x6c pe status 0x70 calibration status register calibration control register 0x74 reserved retry counter discard counter 0x78 our status register 0x7c reserved 0x80:dc pci express capability pe capabilities register next item ptr pe cap id 0xe0 device capabilities 0xe4 device status device control 0xe8 link capabilities 0xec link status link control 0xf0 reserved 0xf4:0xfc byte<3> byte<2> byte<1> byte<0> address marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 57 register description pci-express configuration register file pci express extend ed capabilities advanced error reporting enhanced capability header 0x0100 uncorrectable error status register 0x0104 uncorrectable error mask register 0x0108 uncorrectable error se verity register 0x010c correctable error status register 0x0110 correctable error mask register 0x0114 advanced error capabilities and control register 0x0118 header log register 0x011c 0x0120 0x0124 0x0128 reserved 0x012c:0x01fc transaction layer control register 0x0200 transaction layer status register 0x0204 data link layer control register 0x0208 data link layer status register 0x020c pe physical layer control register 0x0210 pe physical layer status register 0x0214 reserved 0x0218:0x021c pe completion timeout register 0x0220 pe flow control register 0x0224 pe ack timer for 1x link 0x0228 pe ack timer for 4x link 0x022c reserved 0x0230:0x0ffc byte<3> byte<2> byte<1> byte<0> address marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 58 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.2 registers of pci header region 3.2.2.1 vendor id register address: 0x00 width [bit]: 16 the pci sig has allocated 0x1148 to marvell? as a unique identifier. reloadable out of the spi flash memory or twsi eeprom. 3.2.2.2 device id register address: 0x02 width [bit]: 16 the device id register is a 16-bit register that uniquely identifies the pci device within the marvell? product line. reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value vendor id register 15:0 identifies marvell as manufacturer of the pci device. ne 0x11ab 0x11ab bit name description write read reset value device id register 15:0 identifies the pci device within marvell?s product line. ne 0x4360 0x4360 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 59 register description pci-express configuration register file 3.2.3 registers of header region 3.2.3.1 command register address: 0x04 width [bit]: 16 all bits are reloadable ou t of the spi flash memory or twsi eeprom, except for fixed value bits. bit name description write read reset value command register 15:11 reserved 10 intdis disables the device from asserting intx#. 1 = disables the assertion of its intx# sig- nal. 0 = enables the assertion of its intx# sig- nal. refer to msi enable bit. if msi enable bit is set to 1, device is prohibited from using in- tx#. yes aw 0 9 reserved ne 0 0 8 serren 1= enables reporting of non-fatal and fatal errors to the root complex. note that errors are reported if enabled ei- ther through this bit or through the pci-ex- press specific bits in the device control register yes aw 0 7 reserved not applied to pci-express. fixed value 0. ne 0 0 6 perren parity error report response enable. 1 = parity error reporting is enabled 0 = parity error reporting is disabled. yes aw 0 5:3 reserved ne 0 0 2 bmen bus master enable controls the ability of a pci express agent to issue memory and i/o read/write re- quests. 1= bus master accesses are enabled, 0 =bus master accesses are disabled. yes aw 0 1:0 reserved marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 60 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.3.2 status register address: 0x06 width [bit]: 16 all bits are reloadable out of t he spi flash memory or twsi eeprom , except for fixed value bits. bit name description write read reset value status register 15 perr parity error. 1: this bit is set by a device whenever it re- ceives a poisoned tlp, regardless of the state of the parity error enable bit. sh value 0 14 serr signaled serr# . 1: this bit is set when a device sends an err_fatal or err_nonfatal mes- sage, and the serren bit in the com- mand register is 1. sh value 0 13 rmabort received master abort. 1: this bit is set when a requestor receives a completion with unsupported request completion status. sh value 0 12 rtabort received target abort. 1: this bit is set when a requestor receives a completion with completer abort com- pletion status. sh value 0 11:9 reserved 8 dataperr data parity error detected. 1: this bit is set by a requestor if its parity error enable bit is set when either of the following two conditions occur: - requestor receives a completion marked poisoned - requestor poisons a write request. sh value 0 7:5 reserved ne 0 0 4 newcap new capabilities bit 1: new capabilities list implemented 0: new capabilities list not implemented ne 1 1 3 intsta 1: indicates that an intx interrupt message is pending internally to the device. ne value 0 2:0 reserved marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 61 register description pci-express configuration register file 3.2.3.3 revision id register address: 0x08 width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom 3.2.3.4 class code register address: 0x09 width [bit]: 3 x 8 the class code register is used to identify the generic fu nction of the pci device. the register consists of three byte-size fields. the subclass register is re loadable out of the spi flas h memory or twsi eeprom. bit name description write read reset value revision id register 7:0 specifies the pci device revision number/ rev. 0.0. ne 0x00 0x00 bit name description write read reset value programming interface register, lower byte 7:0 specifies the programming interface. fixed value = 0 ne 0 0 bit name description write read reset value sub-class register, middle byte 7:0 identifies the network controller as an ?ethernet controller?. ne 0x00 0x00 bit name description write read reset value base-class register, upper byte 7:0 broadly classifies the function of the pci device as network controller. fixed value = 0x02 ne 0x02 0x02 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 62 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.3.5 cache line register address: 0x0c width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom (not recommended). 3.2.3.6 latency timer register address: 0x0d width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom (not recommended). 3.2.3.7 header type register address: 0x0e width [bit]: 8 bit name description write read reset value cache line size register 7:0 reserved 0 0 0 bit name description write read reset value latency timer register 7:0 reserved bit name description write read reset value base-class register 7:0 reserved marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 63 register description pci-express configuration register file 3.2.3.8 built-in self test register (bist) address: 0x0f width [bit]: 8 bit name description write read reset value built-in self test register 7:0 bist is not supported . fixed value = 0. ne 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 64 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.3.9 base address register (1st) address: 0x010 width [bit]: 2 x 32 the 1st base address register uses two 32-bit registers that determine the location of the pci device in memory space, if memory mapping is enabled. reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value base address register (1st)/lower (address: 0x010, width [bit]: 32) 31:14 lower mem- base address 18 bits of lower mem base address. yes aw 0 13:4 memsize memory size requirements. fixed value 0: memory space requirement of 16384 bytes. ne 0 3 prefen prefetch enable. fixed value 0: prefetching is not allowed. (memory write byte merging is not tolera- ble). ne 0 2:1 memory type memory type. 0b00: base register is 32 bits wide, and mapping can be done anywhere in the 32-bit memory space. 0b10: base register is 64 bits wide and can be mapped anywhere in the 64-bit ad- dress space. memory type may be reloaded out of the spi flash memory or twsi eeprom (fur- ther memory types). ne 0x02 0x02 0 memspace memory space indicator. fixed value = 0: this base address regis- ter describes a memory base address. ne 0 base address register (1st)/upper (address: 0x014, width [bit]: 32) 31:0 upper mem- base upper 32 bits of memory base address. yes aw 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 65 register description pci-express configuration register file 3.2.3.10 base addr ess register (2nd) address: 0x018 width [bit]: 32 the 2nd base address register determines the location of the pci device in the i/o space. reloadable out of the spi flash memory or twsi eeprom. if en io mapping (in our register 1, bit 23) is disabled, this location is treated like reserved locations. 3.2.3.11 subsystem ve ndor id register address: 0x02c width [bit]: 16 the subsystem vendor id register may be used for cust omizing oem versions. the subsystem vendor id is allo- cated by the pci sig. reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value base address register (2nd) 31:8 iobase i/o base address most significant 24 bits. yes aw 0 7:2 iosize i/o size requirements. fixed value 0x0: i/o space requirement of 256 bytes. ne 0 1 reserved 0 iospace i/o space indicator. 1: this base address register describes an i/o base address. ne 1 1 bit name description write read reset value subsystem vendor id register 15:0 subsystem ven- dor id identifies the subsystem vendor. must be a valid non-zero value. ne 0x11ab 0x11ab marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 66 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.3.12 subsystem id register address: 0x02e width [bit]: 16 the subsystem id register may be used for customizing oem versions. reloadable out of the spi flash memory or twsi eeprom. should be reloaded from spi flash memory or twsi eepr om with the subsystem id of the related manufactur- ing option. 3.2.3.13 expansion ro m base address register address: 0x030 width [bit]: 32 the expansion rom base address register is a 32-bit register that determines the base address and size infor- mation of the expansion rom. within the spi flash memory 96 kb may be used for boot code. reloadable out of the spi flash memory or twsi eeprom. if en eprom (in our register 1 , bit 22) is disabled, this location is treated like reserved locations. bit name description write read reset value subsystem id register 15:0 subsystem id identifies the subsystem. must be a valid non-zero value. (default value: device id) ne aw 0x4360 bit name description write read reset value expansion rom base address register 31:17 rombase rom base address significant 15 bits. yes aw 0 16:14 rombase/size treated as rombase or romsize depend- ing on settings of pagesize ( our register 1 , bits 21:20). yes ne aw 0 0 13:11 romsize rom size requirements. fixed value 0: memory space requirement of 16 kb or higher. ne 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 67 register description pci-express configuration register file 3.2.3.14 new capabilities pointer (new cap ptr) address: 0x034 width [bit]: 8 the new capabilities pointer register is a 8-bit register pointing to the first element in the new capabilities list. reloadable out of the spi flash memory or twsi eeprom. 10:1 reserved 0 romen address decode enable. read/write accessible. 0: the device?s expansion rom address space is disabled. 1: and memen =1 ( command register , bit 1), the device?s expansion rom ad- dress space is enabled. yes aw 0 bit name description write read reset value new capabilities pointer register 7:0 new capabili- ties pointer points to the new capabilities list ne 0x48 0x48 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 68 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.3.15 interrupt line register address: 0x03c width [bit]: 8 3.2.3.16 interrupt pin register address: 0x03d width [bit]: 8 bit name description write read reset value interrupt line register 7:0 the interrupt line register is used to com- municate interrupt line routing information. post software writes the routing informa- tion into this register as it initializes and con- figures the system. the value of this register indicates to which input of the system in terrupt controller(s) the device?s interrupt pin is connected. device drivers and operating systems may use this information to determine priority and vector information. the interrupt line register is not modified by the pci device. it has no effect on the operation of the device. yes aw 0 bit name description write read reset value interrupt pin register 7:0 fixed value 0x01:the pci device uses the interrupt pin inta# . ne 0x01 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 69 register description pci-express configuration register file 3.2.3.17 min_gnt register address: 0x03e width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom. 3.2.3.18 max_lat register address: 0x03f width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom. 3.2.4 registers of de vice dependent region 3.2.4.1 our register 1 and our register 2 address: 0x040 width [bit]: 2 x 32 these are the first two used locations in the ?device dependent region?. the default values are chosen for the most common environments. modifications may be handled as manufacturing option, dr iver options, or dedicated configuration software. most of the switches in our register 1 and 2 are not intended for us e at run time. manufact ured pci devices may come up with different settings than defined as reset value (if reloaded out of the spi flash memory or twsi ee- prom). bit name description write read reset value min_gnt register 7:0 this read-only register specifies the pci de- vice?s desired settings for latency timer value. the value specifies - in units of 1/4 micro- seconds - the burst period needed by the pci device assuming a clock rate of 33 mhz. (64 qwords x 30 ns) = 1.92 s 1.92 s/0.25 s=8 ne 0x08 0x08 bit name description write read reset value max_lat register 7:0 reserved ne 0x00 0x00 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 70 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications reloadable out of the spi flash memory or twsi eeprom. the fields marked in column write with ?ne? are writ- able only in testmode. the fields marked with ?yes? are writable in configuration space and with normal accesses to the control register file . bit name description write read reset value our register 1 (address: 0x40, width [bit]: 32) 31 run_pig 1: enable plug in go. ne 1 1 30 dll_dis pci dll disable reset strapping (disable = 1). it is a debug bit (if everything is ok, should be always set to ?1?) ne 1 1 29 reserved 28 phy coma mode set phy to coma mode 1: coma mode 0: normal operation lowest possible power mode, no core clock ne aw 0 27 reserved 26 phy power down mode set phy to power down mode 1: power down mode 0: normal operation phy power down mode (low power mode, only core clock active). yes aw 0 25 reserved 24 en boot boot enable, for software purposes only 1: don?t boot with expansion rom code. 0: boot with expansion rom code yes aw 0 23 en io mapping controls mapping of the control register file to the i/o space (manufacturing op- tion). 1: address decoding for i/o accesses en- abled. 0: any address decoding for i/o accesses is disabled (see also base address regis- ter (2nd) ). ne 1 1 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 71 register description pci-express configuration register file 22 en eprom controls mapping of the spi flash memory to the memory space. 1: address decoding for memory accesses enabled. 0: any address decoding for memory ac- cesses is disabled (see also rom base address register ). ne 0 0 21:20 pagesize<1:0> pagesize/spi flash memory defines the size, which is mapped to the system (see romsize/rombase ). 0x3: 128 kb 0x2: 64 kb 0x1: 32 kb 0x0: 16 kb ne 0x3 0x3 19 reserved 18:16 page reg<2:0> page register selects the page of the spi flash memory space, which is mapped to the system. 0x0: page 0, 0x1: page 1, ... 0x7: page 7 yes aw 0 15 pex_legnat_sel pex: 1: device in pex legacy mode; 0: device in pex native mode. reset by power on reset. yes aw 0 14: 0 reserved yes aw bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 72 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications bit name description write read reset value our register 2 (address: 0x44, width [bit]: 32) 31:24 vpd write thr defines the first address of the writable vpd area in steps of 128 bytes. default value is 128 bytes = address 0x80. last address of writable vpd area is 255. higher addresses belong to the configura- tion data also stored within twsi eeprom. ne 0x01 0x01 23:17 vpd devsel defines the device select byte for the twsi eeprom used for vpd storage. default value is 0b1010000. hint: vpd devsel must not be overwritten via twsi eeprom . this may lead to a complete damage of the board (twsi eeprom must be changed afterwards!!!) ne 0x50 0x50 16:14 vpd rom size defines the size of the assembled twsi eeprom in bytes. 0x0: 256 bytes 0x1: 512 bytes 0x2: 1024 bytes 0x3: 2048 bytes 0x4: 4096 bytes 0x5: 8192 bytes 0x6: 16384 bytes 0x7: 32768 bytes default value is 2048 bytes. if any other size is used, this field must be repro- grammed out of the spi flash memory. due to currently used addressing procedure via twsi bus only applications up to size 2048 bytes are supported. ne 0x3 0x3 13:0 reserved marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 73 register description pci-express configuration register file 3.2.4.2 power management capabi lity id register (pm cap id) address: 0x048 width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.3 power management next item pointer address: 0x049 width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.4 power management capabilities register address: 0x4a width [bit]: 16 reloadable out of the spi flash memory or twsi eeprom. only the bits are mentioned which diff er from the pci configuration file. bit name description write read reset value power management capability id register 7:0 cap id power management capabilities id ne 0x01 0x01 bit name description write read reset value power management next item pointer 7:0 next item ptr pointer to the next item in the capabilities list ne 0x50 0x50 bit name description write read reset value power management capabilities register 15:11 pme support power management event support: speci- fies the power state in which the signal pme# may be asserted. if no vaux is available, bit 15 is forced to zero signaling no pme# support in d3 cold ne marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 74 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 15 1: pme# can be asserted from d3 cold , if vaux is available 0: pme# cannot be asserted from d3 cold , if vaux is not available 1 (0 if no vaux) 1 (0 if no vaux) 14 1: pme# can be asserted from d3 hot 1 1 13 1: pme# can be asserted from d2 12 1: pme# can be asserted from d1 1 1 11 1: pme# can be asserted from d0 1 1 10 d2 support d2 support 1: the pci device supports d2 power man- agement state. ne 9 d1 support d1 support 1: the pci device supports d1 power man- agement state. ne 1 1 8:6 reserved reserved, but reloadable out of the spi flash memory or twsi eeprom for changes in the pci specification. ne 0b000 0b000 5 dsi device specific initialization: 1: the pci device requires device specific initialization 0: the pci device does not require device specific initialization ne 0 0 4:3 reserved 2:0 version the pci device complies with revision 1.1 of the pci power management interface specification ne 0x2 0x2 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 75 register description pci-express configuration register file 3.2.4.5 power management control/status register address: 0x04c width [bit]: 16 reloadable out of the spi flash memory or twsi eeprom. the 16 2-bit data scale fields and the 16 8-bit data register values that can be selected by the data select field, are reloadable out of the spi flash memory or twsi eeprom by writin g complete 32-bit wide sets of ( data se- lect , data scale , data ) to the power management control/status and data register . warning: to modify the contents of any data scale or data field the data scale field must always be written with the desired data select value in the same 32-bit access! bit name description write read reset value power management control/status register 15 pme status 1: indicates that pme# has been asserted by the pci device. reset by power on re- set and when written with 1. sh value 0 14:13 data scale indicates the scaling factor to be used when interpreting the value of the data register . the read value depends on the setting of the data select field. ne value 0b01 12:9 data select this 4-bit field is used to select which data is to be reported through the data register and data scale field. yes aw 0 8 pme en 1: enables pme# generation. reset by power on reset yes aw 0 7:2 reserved 1:0 power state controls the power management state of the pci device. the pci device supports all power management states. yes aw 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 76 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.6 power management data register address: 0x04f width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.7 power management data table data and data scale are hidden registers accessible through the power management control/status register (data select). data scale is writable by the eprom loader by writing to power management control/status register. data is writable by the eprom loader by writing to power management data register. data and data scale are reloaded from the spi flash memory or twsi eeprom with valu es matching the man- ufacturing option. see ?spi flash memory reloads? in the pci device?s application specification?. bit name description write read reset value power management data register 7:0 data this read-only register is used to report the state dependent data requested by the data select field. the value of this register is scaled by the value reported by the data scale field. ne value see power man- age- ment data ta b l e marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 77 register description pci-express configuration register file 3.2.4.8 vpd capability id register (vpd cap id) address: 0x050 width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.9 vpd next item pointer address: 0x051 width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom. value in data select meaning data (8 bit) reset value data scale (2 bit) reset value [watt] with reset values 0 d0 power consumed 0x13 0b01 1.9 1 d1 power consumed 0x0c 0b01 1.2 2 d2 power consumed 0x0c 0b01 1.2 3 d3 power consumed 0x0c 0b01 1.2 4 d0 power dissipated 0x13 0b01 1.9 5 d1 power dissipated 0x0c 0b01 1.2 6 d2 power dissipated 0x0c 0b01 1.2 7 d3 power dissipated 0x0c 0b01 1.2 8:15 for multifunction devic- es only 000 bit name description write read reset value vpd capability id register 7:0 cap id vpd capabilities id ne 0x03 0x03 bit name description write read reset value vpd next item pointer 7:0 next item ptr pointer to the next item in the capabilities list. ne 0x5c 0x5c marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 78 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.10 vpd address register address: 0x052 width [bit]: 16 the vpd address register and the vpd data register control a twsi interface, which runs a 100 khz protocol to an external twsi eeprom. reloadable out of the spi flash memory or twsi eeprom. also writable in i/o space. 3.2.4.11 vpd data register address: 0x054 width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. also writable in i/o space. bit name description write read reset value vpd address register 15 flag starts the vpd data transfers, determines its direction and signal s its completion by being toggled. if written 1, a vpd write is started. set to 0 after completion. if written 0, a vpd read is started. set to 1 after completion. exec value 0 14:0 vpd address address of the vpd contents to be written / read. yes aw 0x00 bit name description write read reset value vpd data register 31:0 vpd data must be written before vpd address regis- ter for vpd write. contains vpd read data after completion of vpd read. yes aw 0x00 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 79 register description pci-express configuration register file 3.2.4.12 twsi eeprom control register address: 0x05a width [bit]: 16 the twsi eeprom co ntrol register controls the twsi eeprom loader. reloadable out of the spi flash memory and can be written in test mode. 3.2.4.13 msi capabi lity id register (msi cap id) address: 0x05c width [bit]: 8 the device is capable of message signaled interrupt (msi) handling. reloadable out of the spi flash memory or twsi eeprom. 3.2.4.14 msi next item pointer address: 0x05d width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value twsi eeprom control register 15 flag starts and stops the data transfer. if written 1, the twsi eeprom loader is started. if written 0, the twsi eeprom loader is stopped. ne 0 0 14:0 twsi eeprom address start address for twsi eeprom loader. should be minimum 256 (0x100) and in 8 byte steps. ne 0x100 0x100 bit name description write read reset value msi capability id register 7:0 cap id msi capabilities id ne 0x05 0x05 bit name description write read reset value msi next item pointer 7:0 next item ptr pointer to the next item in the capabilities list. ne 0x6c pex: 0x0e marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 80 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.15 msi message control address: 0x05e width [bit]: 16 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value msi message control 15:8 reserved ne 0 0 7 64 bit addr capable 1: this device is capable of generating a 64- bit message address 0: the device is not capable of generating a 64-bit message address ne 1 1 6:4 multiple mes- sage enable defines the number of allocated messages 0b000: 1 the implementation supports one allocated message. yes value 0 3:1 multiple mes- sage capable system software reads this field to deter- mine the number of requested messages. 0b000: 1 there is one requested message. 0 msi enable 1: msi is used to request service. inta# is disabled. 0: inta# is used to request service msi is disabled marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 81 register description pci-express configuration register file 3.2.4.16 msi message address address: 0x060 width [bit]: 2 x 32 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value msi message lower address (address: 0x060, width [bit]: 32) 31:2 system-specified message address if msi enable is set, the contents of this register specify the dword aligned ad- dress for the msi memory write transac- tion . yes value 0x00 1:0 reserved msi message upper address (address: 0x064, width [bit]: 32) 31:0 system-specified message upper address if msi enable is set, the contents of this register (if non-zero) specify the upper 32- bits of a 64-bit message address if the contents of this register are zero, the device uses the 32 bit address specified by the msi message lower address . yes value 0x00 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 82 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.17 msi message data address: 0x068 width [bit]: 16 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value msi message data 31:16 reserved 15:0 message data system-specified message. if msi enable is set, the message data is driven onto the lower word of the memory write transaction?s data phase. the multiple message enable field (bits 6:4 of the message control register ) defines the number (only one message sup- ported by the chip) yes value 0x00 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 83 register description pci-express configuration register file 3.2.4.18 pci express status address: 0x070 width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom 3.2.4.19 calibration c ontrol/status register address: 0x074, 0x076width [bit]:16 not applied to pci-express. fixed value 0. 3.2.4.20 discard counter, retry counter address: 0x078, 0x07awidth [bit]:16, 8 not applied to pci-express. fixed value 0. bit name description write read reset value pci express status 31:30 reserved 29:16 not applied to pci-express. fixed value 0. ne 0 0 15:8 request id (bus number) request id is the combination of a re- quester?s bus number, device number, and function number that un iquely identifies the requester. the bus number is updated with each con- figuration write transaction. ne value 0 7:3 request id (device number) request id is the combination of a re- quester?s bus number, device number, and function number that un iquely identifies the requester. the device number is updated with each configuration write transaction. ne value 0 2:0 request id (function num- ber) the function number is part of the re- quester id. fixed value: 0b000 ne 0x00 0x00 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 84 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.21 our status register address: 0x07c width [bit]: 32 bit name description write read reset value our status register 31 reserved ne value 30 reserved ne value 29:28 reserved ne value 27 reserved ne value 26 reserved ne value 0 25:24 dll err dll status indication: 0x0:no error 0x1:delay line pointer at start, and down count 0x2:delay line pointer at end, and up count 0x3:reserved read only register ne value 23:20 dll row dll row counters values. calculate the taps number, using row and column num- bers. read only register ne value 19:16 dll col dll column counters values. calculate the taps number, using row and column num- bers. read only register ne value 15:8 reserved 7:0 reserved marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 85 register description pci-express configuration register file 3.2.4.22 pe capability id register (pm cap id) address: 0x0e0 width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.23 pe next item pointer address: 0x0e1 width [bit]: 8 reloadable out of the spi flash memory or twsi eeprom 3.2.4.24 pe capab ilities register address: 0x0e2 width [bit]: 16 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value pe capability id register 7:0 cap id pci express capabilities id ne 0x10 0x10 bit name description write read reset value pe next item pointer 7:0 next item ptr pointer to the next pci capability structure. ne 0 0 bit name description write read reset value pe capabilities register 15:14 reserved 13:9 interrupt mes- sage number if this function is allocated more than one msi interrupt number, th is register is re- quired to contain the offset between the base message data and the msi message that is generated when any of the status bits in either the slot status register or the root port status register of this capability struc- ture are set. hardware is required to update this field so that it is correct if the number of msi mes- sages assigned to the device changes. ne 0 0 8 reserved marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 86 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.25 device capa bilities register address: 0x0e4 width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. 7:4 device/port type indicates the type of pci express logical device. defined encodings are: 0b0000: pci express endpoint device 0b0001: legacy pci express endpoint de- vice 0b0100: root port of pci express root complex 0b0101: upstream port of pci express switch 0b0110: downstream port of pci express switch 0b0111: pci express-to-pci/pci-x bridge 0b1000: pci/pci-x to pci express bridge. ne 1 1 3:0 capability version pci express capability structure version number. ne 0x01 0x01 bit name description write read reset value device capabilities register 31:28 reserved 27:26 captured slot power limit scale it specifies the scale used for the slot pow- er limit value. range of values: 0b00: 1.0x 0b01: 0.1x 0b10: 0.01x 0b11: 0.001x ne 0 0 25:18 captured slot power limit value specifies the upper limit on power supplied by slot in combination with the slot power limit scale value. power limit (in watts) ca lculated by multiply- ing the value of this field by the value in the slot power limit scale field. ne 0 0 17:15 reserved bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 87 register description pci-express configuration register file 14 power indicator present 1: indicates that a power indicator is imple- mented on the pci device. ne 0 0 13 attention indica- tor present 1: indicates that an attention indicator is im- plemented on the pci device. ne 0 0 12 attention but- ton present 1: indicates that an attention button is im- plemented on the pci device. ne 0 0 11:9 endpoint l1 acceptable latency this field indicates the acceptable latency that an endpoint can withstand due to the transition from l1 state to the l0 state. power management software uses the re- ported l1 acceptable latency number for comparison with the l1 exit latencies re- ported (see below) by all components com- prising the data path from this endpoint to the root complex root port to determine whether active state link pm l1 entry can be used with no loss of performance. de- fined encodings are: 0b000: less than 1 s 0b001: 1 s to less than 2 s 0b010: 2 s to less than 4 s 0b011: 4 s to less than 8 s 0b100: 8 s to less than 16 s 0b101: 16 s to less than 32 s 0b110: 32 s up to 64 s 0b111: more than 64 s ne 0b111 0b111 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 88 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 8:6 endpoint l0s acceptable latency this field indicates the acceptable total la- tency that an endpoint can withstand due to the transition from l0s state to the l0 state. power management software uses the re- ported l0s acceptable latency number for comparison with the l0s exit latencies re- ported by all components comprising the data path from this endpoint to the root complex root port to determine whether active state link pm l0s entry can be used with no loss of performance. defined encod- ings are: 0b000: less than 64 ns 0b001: 64 ns to less than 128 ns 0b010: 128 ns to less than 256 ns 0b011: 256 ns to less than 512 ns 0b100: 512 ns to less than 1 s 0b101: 1 s to less than 2 s 0b110: 2 s up to 4 s 0b111: more than 4 s ne 0b111 0b111 5 extended tag field supported this field indicates the maximum supported size of the tag field. 1: 8-bit tag field supported 0: 5-bit tag field supported ne 0 0 4:3 phantom func- tions supported this field indicates the support of using un- claimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called phantom functions) with the tag identifier. note that phantom function support for the device must be enabled by the correspond- ing control field in the device control regis- ter. not supported according to bit 9 of device control register. ne 0 0 2:0 max_payload_si ze supported this field indicates the maximum payload size in bytes that the device can support for tlps. defined encodings are: 0b000: 128 b maximum payload size ne 0 0 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 89 register description pci-express configuration register file 3.2.4.26 device control register address: 0x0e8 width [bit]: 16 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value device control register 15 reserved 14:12 max_read_requ est_size this field sets the maximum read request size for the device as a requester in bytes. the device must not generate read re- quests with size exceeding the set value. defined encodings for this field are: 0b000: 128 b max read request size 0b001: 256 b max read request size 0b010: 512 b max read request size 0b011: 1024 b max read request size 0b100: 2048 b max read request size 0b101: 4096 b max read request size 0b110: reserved 0b111: reserved yes aw 0x02 11 enable no snoop 1: the device is permitted to set the no snoop bit in the requester attributes of initiated transactions that do not re- quire hardware enforced cache coheren- cy. fixed value 0, not supported. ne 0 0 10 auxiliary (aux) power pm enable 1: enables a device to draw aux power in- dependent of pme aux power. reset by power on reset. ne aw 1 9 phantom func- tions enable 1: enables a device to use unclaimed func- tions as phantom functions to extend the number of outstanding transaction identi- fiers. fixed value 0, not supported. ne 0 0 8 extended tag field enable 1: enables a device to use an 8-bit tag field as a requester. fixed value 0, not supported. ne 0 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 90 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 7:5 max_payload_si ze this field sets the maximum tlp payload size for the device. as a receiver, the device must handle tlps as large as the set value; as transmitter, the device must not generate tlps exceeding the set value. permissible values for programming are in- dicated by the max_payload_size support- ed in the device capabilities register. defined encodings for this field are: 0b000: 128 b maximum payload size device supports only 128 bytes. yes aw 0 4 enable relaxed ordering 1: the device is permitted to set the re- laxed ordering bit in the attributes field of initiated transactions that do not require strong write ordering. fixed value 0. ne 0 0 3 unsupported request report- ing enable this bit controls reporting of unsupported requests when set. yes aw 0 2 fatal error reporting enable this bit controls reporti ng of fatal errors. yes aw 0 1 non-fatal error reporting enable this bit controls reporting of non-fatal er- rors. yes aw 0 0 correctable error reporting enable this bit controls reporting of correctable er- rors. yes aw 0 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 91 register description pci-express configuration register file 3.2.4.27 device status register address: 0x0ea width [bit]: 16 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value device status register 15:6 reserved 5 transactions pending 1: indicates that a device has issued non- posted requests which have not been completed. a device reports this bit cleared only when all completions for any outstanding non-posted requests have been received. ne value 4 aux power detected 1: devices that require aux power report this bit as set if aux power is detected by the device. ne value 3 unsupported request detected 1: indicates that the device received an un- supported request. errors are logged in this register regardless of whether error reporting is enabled or not in the device control register. default value is 0. sh value 0 2 fatal error detected 1: indicates status of fatal errors detected. errors are logged in this register regard- less of whether error reporting is enabled or not in the device control register. for devices supporting advanced error handling, errors are logged in this register regardless of the settings of the correctable error mask register. default value is 0. sh value 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 92 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.28 link capabilities register address: 0x0ec width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. 1 non-fatal error detected 1: indicates status of nonfatal errors detect- ed. errors are logged in this register re- gardless of whether error reporting is enabled or not in the device control reg- ister. for devices supporting advanced error handling, errors are logged in this register regardless of the settings of the correctable error mask register. default value is 0. sh value 0 0 correctable error detected 1: indicates status of correctable errors de- tected. errors are logged in this register regardless of whether error reporting is enabled or not in the device control reg- ister. for devices supporting advanced error handling, errors are logged in this register regardless of the settings of the correctable error mask register. default value is 0. sh value 0 bit name description write read reset value link capabilities register 31:24 port number this field indicates the pci express port number for the given pci express link. hardware initialized. ne value 00 23:18 reserved bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 93 register description pci-express configuration register file 17:15 l1 exit latency this field indicates the l1 exit latency for the given pci express link. the value re- ported indicates the length of time this port requires to complete transition from l1 to l0. defined encodings are: 0b000: less than 1 s 0b001: 1 s to less than 2 s 0b010: 2 s to less than 4 s 0b011: 4 s to less than 8 s 0b100: 8 s to less than 16 s 0b101: 16 s to less than 32 s 0b110: 32 s up to 64 s 0b111: more than 64 s ne 0b111 0b111 14:12 l0s exit latency this field indicates th e l0s exit latency for the given pci express link. the value re- ported indicates the length of time this port requires to complete transition from l0s to l0. defined encodings are: 0b000: less than 64 ns 0b001: 64 ns to less than 128 ns 0b010: 128 ns to less than 256 ns 0b011: 256 ns to less than 512 ns 0b100: 512 ns to less than 1 s 0b101: 1 s to less than 2 s 0b110: 2 s up to 4 s 0b111: reserved ne 0b010 0b010 11:10 active state link pm support this field indicates the level of active state power management supported on the given pci express link. defined encodings are: 0b00: reserved 0b01: l0s entry supported 0b10: reserved 0b11: l0s and l1 supported ne 0b01 0b01 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 94 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.29 link control register address: 0x0f0 width [bit]: 16 reloadable out of the spi flash memory or twsi eeprom. 9:4 maximum link width this field indicates the maximum width of the given pci express link. defined encod- ings are: 0b000000: reserved ne x01 x01 x01 x01 3:0 maximum link speed this field indicates the maximum link speed of the given pci express link. defined en- codings are: 0b0001 2.5 gb/s link. all other encodings are reserved. ne 0x01 0x01 bit name description write read reset value link control register 15:8 reserved 7 extended sync 1: forces extended tr ansmission of fts or- dered sets in fts and extra ts2 at exit from l1 prior to entering l0. this mode provides external devices monitoring the link time to achieve bit and symbol lock before the link enters l0 state and re- sumes communication. yes aw 0 6 common clock configuration 1: indicates that this component and the component at the opposite end of this link are operating with a distributed common reference clock. 0: indicates that this component and the component at the opposite end of this link are operating with asynchronous refer- ence clock. components utilize this common clock con- figuration information to report the correct l0s and l1 exit latencies. yes aw 0 5:4 reserved bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 95 register description pci-express configuration register file 3.2.4.30 link status register address: 0x0f2 width [bit]: 16 reloadable out of the spi flash memory or twsi eeprom. 3 read comple- tion boundary (rcb) it determines the naturally aligned address boundaries on which a read request may be serviced with multiple completions. encodings are: 0b0: 64 bytes 0b1: 128 bytes device supports only 128 bytes yes aw 1 2 reserved 1:0 active state link pm control this field controls the level of active state pm supported on the given pci express link. defined encodings are: 0b00: disabled 0b01: l0s entry supported 0b10: reserved 0b11: l0s and l1 entry supported yes aw 0 bit name description write read reset value link status register 15:13 reserved 12 slot clock con- figuration 1: indicates that th e component uses the same physical refere nce clock that the platform provides on the connector. 0: 25 mhz reference clock. if the device uses an independent clock irrespective of the presence of a reference on the con- nector. hardware initialized ne 1 1 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 96 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 11 link training this read-only bit indicates that link training is in progress; hardware clears this bit once link training is complete. this field is not applicable and reserved for endpoint devices and upstream ports of switches. for debug purpose, not used for yukon ec ne value 10 training error this read-only bit indicates that a link train- ing error occurred. this field is not applicable and reserved for endpoint devices and upstream ports of switches. this bit is cleared by hardware upon suc- cessful training of the link to the l0 link state. for debug purpose, not used for yukon ec ne value 9:4 negotiated link width this field indicates the negotiated width of the given pci express link. defined encod- ings are: 0b000001: x1 all other encodings are reserved. ne value 3:0 link speed this field indicates the negotiated link speed of the given pci express link. de- fined encodings are: 0b0001: 2.5 gb/s pci express link all other encodings are reserved. ne value bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 97 register description pci-express configuration register file 3.2.4.31 advanced error reporti ng enhanced capability header address: 0x0100width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.32 uncorrectable error status/mask/severity register address: 0x0104:0x010c width [bit]:3 x 32 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value advanced error reporting enhanced capability header 31:20 next capability offset this field is a pci- sig defined id number that indicates the natur e and format of the extended capability. ne 0 0 19:16 capability ver- sion this field is a pci-sig defined version num- ber that indicates the version of the capabil- ity structure present. ne 0x01 0x01 15:0 pci express extended capa- bility id this field contains the offset to the next pci express capability structure. ne 0x01 0x01 bit name description write read reset value uncorrectable error status register 31:21 reserved 20 unsupported request error 1: indicates - received unsupported tlp type or - received unsupported message codes or - failed address decoding on received tlp. reset by pex sticky reset sh value 0 19 ecrc error not supported, fixed value 0. ne 0 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 98 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 18 malformed tlp 1: indicates - received tlp with data payload size larger than 128 b (max_payload_size) or - received tlp with undefined type field value or - received tlp with illegal format field value or - received tlp with data payload size dif- ferent from expected according to the length field or - received tlp with uninitialized vc (dif- ferent than vc-0) or - received request with address/length combination crossing 4 kb boundary or - received tlp with td = 1 but without tlp digest. reset by pex sticky reset sh value 0 17 receiver over- flow not supported, fixed value 0. ne 0 0 16 unexpected completion 1: indicates received unexpected comple- tion tlp. completion does not corre- spond to one of the outstanding non- posted requests. reset by pex sticky reset sh value 0 15 completer abort not supported, fixed value 0. sh 0 0 14 completion tim- eout 1: indicates outstanding non-posted re- quest to pci-express has expired. reset by pex sticky reset sh value 0 13 flow control protocol error 1: indicates flow control protocol error sta- tus. reset by pex sticky reset sh 0 0 12 poisoned tlp 1: indicates poisoned tlp received. reset by pex sticky reset sh value 0 11:5 reserved 4 data link proto- col error 1: indicates reception of an acknowledge with out of range acknak_seq_num (ack/nak sequence number). reset by pex sticky reset sh value 0 3:1 reserved 0 training error not supported, fixed value 0. sh 0 0 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 99 register description pci-express configuration register file uncorrectable error mask register 31:21 reserved 20 unsupported request error 1: not send error message to rc, not lock first error pointer, not logged in the header log register. reset by pex sticky reset yes aw 0 19 ecrc error not supported, fixed value 0. ne 0 0 18 malformed tlp 1: not send error message to rc, not lock first error pointer, not logged in the header log register. reset by pex sticky reset yes aw 0 17 receiver over- flow not supported, fixed value 0. ne 0 0 16 unexpected completion 1: not send error message to rc, not lock first error pointer, not logged in the header log register. reset by pex sticky reset yes aw 0 15 completer abort not supported, fixed value 0. ne 0 0 14 completion tim- eout 1: not send error message to rc, not lock first error pointer, not logged in the header log register. reset by pex sticky reset yes aw 0 13 flow control protocol error 1: not send error message to rc, not lock first error pointer, not logged in the header log register. reset by pex sticky reset yes aw 0 12 poisoned tlp 1: not send error message to rc, not lock first error pointer, not logged in the header log register. reset by pex sticky reset yes aw 0 11:5 reserved 4 data link proto- col error 1: not send error message to rc, not lock first error pointer, not logged in the header log register. reset by pex sticky reset yes aw 0 3:1 reserved 0 training error not supported, fixed value 0. ne 0 0 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 100 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications uncorrectable error severity register 31:21 reserved 20 unsupported request error non-fatal reset by pex sticky reset yes aw 0 19 ecrc error severity not supported, fixed value 0. ne 0 0 18 malformed tlp fatal reset by pex sticky reset yes aw 1 17 receiver over- flow fatal not supported, fixed value 1. ne 1 1 16 unexpected completion non-fatal reset by pex sticky reset yes aw 0 15 completer abort non-fatal not supported, fixed value 0. yes aw 0 14 completion tim- eout non-fatal reset by pex sticky reset yes aw 0 13 flow control protocol error non-fatal reset by pex sticky reset yes aw 1 12 poisoned tlp non-fatal reset by pex sticky reset yes aw 0 11:5 reserved 4 data link proto- col error fatal reset by pex sticky reset yes aw 1 3:1 reserved 0 training error not supported, fixed value 1. ne 1 1 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 101 register description pci-express configuration register file 3.2.4.33 correctable error status/mask register address: 0x0110:0x0114width [bit]:2 x 32 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value correctable error status register 31:13 reserved 12 replay timer timeout 1: indicates replay timer expired, replay_num did not rollover. reset by pex sticky reset sh value 0 11:9 reserved 8 replay_num rollover 1: indicates 4 consecutive replays were transmitted. reset by pex sticky reset sh value 0 7 bad dllp 1: indicates - lcrc error detected in received dllp or - dllp is larger than 6 b. reset by pex sticky reset sh value 0 6 bad tlp 1: indicates - lcrc error detected in received tlp or - sequence number error detected in re- ceived tlp. reset by pex sticky reset sh value 0 5:1 reserved 0 receiver error 1: indicates - overflow/underrun or - 8 b/10 b decode error or - disparity error or - framing error - stp or sdp without end or edb to previous frame or - framing error - unexpected k code (spe- cial symbols for framing and link manage- ment, refer to pci express base specification) in a middle of a frame (not end or edb). reset by pex sticky reset sh value 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 102 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications correctable error mask register 31:13 reserved 12 replay timer timeout 1: not send error message to rc reset by pex sticky reset yes aw 0 11:9 reserved 8 replay_num rollover 1: not send error message to rc reset by pex sticky reset yes aw 0 7 bad dllp 1: not send error message to rc reset by pex sticky reset yes aw 0 6 bad tlp 1: not send error message to rc reset by pex sticky reset yes aw 0 5:1 reserved 0 receiver error 1: not send error message to rc yes aw 0 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 103 register description pci-express configuration register file 3.2.4.34 advanced error capa bilities and control register address: 0x0118width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value advanced error capabilities and control register 31:9 reserved 8 ecrc check enable 1: enables ecrc checking. not supported, fixed value 0. ne 0 0 7 ecrc check capable 1: indicates that the device is capable of checking ecrc. not supported, fixed value 0. ne 0 0 6 ecrc genera- tion enable 1: enables ecrc generation. not supported, fixed value 0. ne 0 0 5 ecrc genera- tion capable 1: indicates that the device is capable of generating ecrc. not supported, fixed value 0. ne 0 0 4:0 first error pointer the first error pointer is a read-only regis- ter that identifies the bit position of the first unmasked error reported in the uncorrect- able error status register. note that the reset value 0x1f corresponds to the bit position of the reserved register bit 31 in uncorrectable error status regis- ter. reset by pex sticky reset ne value 0x1f marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 104 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.35 header log register address: 0x011c:0x0128width [bit]:4 x 32 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.36 transaction layer control register address: 0x0200width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.37 transaction la yer status register address: 0x0204width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value header log register 127:0 header log header of tlp associated with an error if this error is the first unmasked uncorrect- able error detected. reset by pex sticky reset ne value 0 bit name description write read reset value transaction layer control register 31:5 reserved 1:0 max_outstand maximum outstanding np requests. 0x0: 1 request 0x1: 2 requests 0x2: 4 requests 0x3: 8 requests yes aw 0x03 bit name description write read reset value transaction layer status register 31:0 reserved marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 105 register description pci-express configuration register file 3.2.4.38 data link l ayer control register address: 0x0208width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.39 data link layer status register address: 0x020cwidth [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.40 pe physical l ayer control register address: 0x0210width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value data link layer control register 31:0 reserved bit name description write read reset value data link layer status register 31:0 reserved bit name description write read reset value pe physical layer control register 31:16 reserved 15:8 n_fts number of fts ordered-sets needed by the device for l0s exit to l0. advertised in transmitted tss. yes aw 0x14 7:0 reserved marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 106 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.2.4.41 pe physical layer status register address: 0x0214width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.42 pe completion timeout register address: 0x0220width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value pe physical layer status register 31:0 reserved bit name description write read reset value pe completion ti meout register 31:16 reserved 15:0 cmptothrshld completion timeout threshold. controls the size of the completion timeout time interval. note: time scale: 256 * symbol_time = 1 s 0x0: disabled. no timeout mechanism on np tlps. minimum value: 40 (40 s) maximum value: 25 k (25 ms) yes aw 0x2710 (10000 or 10 ms) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 107 register description pci-express configuration register file 3.2.4.43 pe flow control register address: 0x0224width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. 3.2.4.44 pe ack timer for 1x link address: 0x0228width [bit]: 32 reloadable out of the spi flash memory or twsi eeprom. bit name description write read reset value pe flow control register 31:24 phinitfc posted headers flow control credit initial value. yes aw 0x02 23:16 nphinitfc non-posted headers flow control credit initial value. yes aw 0x02 15:8 chinitfc completion headers flow control credit initial value. yes aw 0 7:0 fcupdateto flow control update timeout. controls the flow control update interval period. note: time scale: 64 * symbol_time = 250 ns. 0x0: disabled. no timeout mechanism on update fc. minimum value: 120 (30 s) maximum value: 180 (45 s) yes aw 0x078 (120 or 30 s) bit name description write read reset value pe ack timer for 1x link 31:16 ackrplytox1 ack replay timer timeout value for x1. note: timescale: symbol_time = 4 ns minimum value: 711 (2.84 s) maximum value: 64k-1 (262 s) yes aw 0x0320 (800) 15:0 acklattox1 ack latency timer timeout value for x1 link. used when phy link width auto-negoti- ation result is x1. note: time scale: symbol_time = 4 ns minimum value: 4 (16 ns) maximum value: 237 (948 ns) yes aw 0x04 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 108 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3 control register file the control register file demonstrates all registers acce ssible to the host, independent of their specific physical location. it may be mapped in the 32-bit i/o space as we ll as in the 32-bit memory space depending on base address register (1st) and base address register (2nd). mapping to the i/o space may be disabled by en io mapping . write operations to reserved or no t implemented registers are completed no rmally on the bus and the data is dis- carded. read operations to reserved or not implemented registers are completed no rmally on the bus, read data is unde- fined. if sw reset is set, it is not recommended to access the control register file except for accessing the control register (all internal or external devices are in reset state). write operations are completed normally on the bus and the data is discarded. read operations are completed normally on the bus and a data value of 0 is returned. in order to prevent setup and hold time violations, all signals and/or events routed through read registers are syn- chronized to clk (pci). all signals and/or events routed through inta# are glitch free and, except for those directly related to clk (pci), independent of clk (pci). 3.3.1 overview and address map the table below depicts the layout of the control register file. if the control register file is mapped into the memory space, it cove rs a memory range of 16 kb. all registers may be accessed directly. if the control register file is mapped into the i/o spac e, it covers an i/o range of 256 byte. the 16 kb range of the control register file is segmented into 128 128-byte blocks. block 0 is mapped permanently into the lower half of the 256 byte i/o range. block 0 - 127 are mapped into the upper half of the 256 byte i/o range as defined by the register address port (rap). as a side effect, register addressing with the rap ma y also be used, if the cont rol register file is mapped into the memory space column ?sti? marks registers residing behind the same targ et interface (all registers within the same row separa- tion line). marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 109 register description control register file byte<3> byte<2> byte<1> byte<0> address sti block reserved reserved reserved register address port (rap) 0x0000 0 power control control/status register 0x0004 interrupt source register 0x0008 interrupt mask register 0x000c interrupt hardware error source register 0x0010 interrupt hard ware error mask register 0x0014 special interrupt source register 1 0x0018 special interrupt source register 2 0x001c special interrupt source register 3 0x0020 enter interrupt service routine register 0x0024 leave interrupt service routine register 0x0028 interrupt control register 0x002c reserved (legacy) 0x0030 : 0x005c spi flash memory control register 0x0060 spi flash memory address register 0x0064 spi flash memory data register 0x0068 spi flash memory vendor/device id register 0x006c spi flash memory loader configuration register 0x0070 spi flash memory vpd configuration register 0x0074 spi flash memory opcode 1 register 0x0078 spi flash memory opcode 2 register 0x007c block window register <31:0> note: if rap = 1, read values are zero, write cycles have no effect 0x0080 : 0x00fc 1 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 110 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications mac addr_1<3> mac addr_1<2> mac addr_1<1> mac addr_1<0> 0x0100 2 reserved reserved mac addr_1<5> mac addr_1<4> 0x0104 reserved reserved mac addr_2<5> mac addr_2<4> 0x010c mac address for maintenance mac addr_3<3> mac addr_3<2> mac addr_3<1> mac addr_3<0> 0x0110 reserved reserved mac addr_3<5> mac addr_3<4> 0x0114 chip id chip revision pmd type connector type 0x0118 eprom<3> eprom<2> hw resources eprom<1> clock gating reg- ister eprom<0> ram size 0x011c reserved clock divider value clock divider con- trol 0x120 reserved (legacy) 0x0124 : 0x012c irq timer irq timer init value 0x0130 sti irq timer 0x0134 reserved reserved irq timer test irq timer control 0x0138 reserved 0x013c irq moderation timer irq moderation timer init value 0x0140 sti irq moderation timer 0x0144 reserved reserved irq moderation timer test irq moderation timer control 0x0148 sti interrupt moderation mask register 0x014c interrupt hardware error moderation mask register 0x0150 reserved 0x0154 byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifica tion: proprietary information page 111 register description control register file 2 reserved test control reg 2 test control reg 1 0x0158 general purpose io register 0x015c twsi (hw) control register 0x0160 twsi (hw) data register 0x0164 twsi (hw) irq register 0x0168 twsi (sw) register 0x016c pex phy address register pex phy data register 0x0170 reserved 0x0174 reserved (legacy) 0x0178 reserved 0x017c ram random registers 3 ram address 0x0180 sti ram data port/lower dword 0x0184 ram data port/upper dword 0x0188 reserved 0x018c ram interface registers timeout init value 3 (read sm rx1) timeout init value 2 (write sm tx/s1) timeout init value 1 (write sm tx/a1) timeout init value 0 (write sm rx1) 0x190 sti reserved reserved) timeout init value 5 (read sm tx/s1) timeout init value 4 (read sm tx/a1) 0x0194 reserved 0x0198 reserved timeout timer 0x019c reserved timer test ram interface control 0x01a0 reserved 0x01a4 : 0x01fc 3 byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 112 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications transmit arbiter 4 interval timer init value 0x0200 sti interval timer 0x0204 limit counter init value 0x0208 limit counter 0x020c reserved timer/ counter status timer/ counter te s t timer/ counter control 0x0210 reserved 0x0214 : 0x021c rss key rss key 0 0x0220 rss key 1 0x0224 rss key 2 0x0228 rss key 3 0x022c reserved 0x0230 : 0x027c reserved 0x0294 : 0x029c 5 reserved 0x02b0 : 0x02fc reserved reserved reserved (legacy) 0x0300 : 0x037c 6 pci configuration register file (lower half) 0x0380 : 0x03fc 7 byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifica tion: proprietary information page 113 register description control register file receive queue 8 current receive descriptor receive buffer control receive buffer byte count 0x0400 rss hash checksum 0x0404 receive buffer address, lower dword 0x0408 receive buffer address, upper dword 0x040c receive status word 0x0410 receive timestamp 0x0414 tcp/ip checksum extension tcp checksum 2 tcp checksum 0x0418 start position, tcp checksum 2 s tart position, tcp checksum 0x041c reserved vlan tag 0x0420 reserved done index 0x0424 request address, lower dword 0x0428 request address, upper dword 0x042c reserved request byte count 0x0430 bmu control/status register 0x0434 bmu test register 0x0438 bmu state machine register 0x043c reserved fifo alignment fifo watermark 0x0440 reserved fifo read shadow level fifo read shadow pointer 0x0444 reserved fifo read level reserved fifo read pointer 0x0448 fifo write shadow level fifo write level fifo write shadow pointer fifo write pointer 0x044c byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 114 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications rx prefetch unit 8 prefetch control register 0x0450 reserved last index 0x0454 list start address, low 0x0458 list start address, high 0x045c reserved get index 0x0460 reserved put index 0x0464 reserved 0x0468 : 0x046c fifo write shadow pointer reserved fifo write pointer 0x0470 reserved fifo read pointer 0x0474 master request nbytes reserved fifo watermark 0x0478 fifo shadow level reserved fifo level 0x047c reserved 9 reserved reserved reserved 0x0500 : 0x05fc 10 : 11 byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifica tion: proprietary information page 115 register description control register file asynchronous transmit queue 13 current transmit descriptor transmit buffer control transmit buffer byte count 0x0680 reserved 0x0684 transmit buffer address, lower dword 0x0688 transmit buffer address, upper dword 0x068c transmit status word 0x0690 tcp/ip checksum extension reserved tcp sum init value 0x0694 tcp sum start tcp sum write 0x0698 reserved 0x069c reserved vlan tag 0x06a0 reserved done index 0x06a4 request address, lower dword 0x06a8 request address, upper dword 0x06ac reserved request byte count 0x06b0 bmu control/status register 0x06b4 bmu test register 0x06b8 bmu state machine register 0x06bc reserved fifo alignment fifo watermark 0x06c0 reserved fifo write shadow level fifo write shadow pointer 0x06c4 reserved fifo write level reserved fifo write pointer 0x06c8 reserved fifo read level reserved fifo read pointer 0x06cc byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 116 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications txa prefetch unit 13 prefetch control register 0x06d0 reserved last index 0x06d4 list start address, low 0x06d8 list start address, high 0x06dc reserved get index 0x06e0 reserved put index 0x06e4 reserved 0x06e8 : 0x06ec fifo write shadow pointer reserved fifo write pointer 0x06f0 reserved fifo read pointer 0x06f4 master request nbytes reserved fifo watermark 0x06f8 fifo shadow level reserved fifo level 0x06fc byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifica tion: proprietary information page 117 register description control register file receive rambuffer 16 receive rambuffer start address 0x0800 sti receive rambuffer end address 0x0804 receive buffer write pointer 0x0808 receive buffer read pointer 0x080c receive rambuffer upper threshold/pause packets 0x0810 receive rambuffer lower threshold/pause packets 0x0814 receive rambuffer upper threshold/high priority 0x0818 receive rambuffer lower threshold/high priority 0x081c receive rambuffer packet counter 0x0820 receive rambuffer level 0x0824 receive rambuffer control/test 0x0828 reserved 0x082c : 0x087c reserved 17 byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 118 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications reserved 18 reserved 0x0900 sti reserved 0x0904 reserved 0x0908 reserved 0x090c reserved 0x0910 reserved 0x0914 reserved 0x0918 reserved 0x091c reserved 0x0920 reserved 0x0924 reserved 0x0928 reserved 0x092c : 0x093c reserved reserved 0x0940 sti reserved 0x0944 reserved 0x0948 reserved 0x094c reserved 0x0950 : 0x095c reserved 0x0960 reserved 0x0964 reserved 0x0968 reserved 0x096c : 0x097c byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifica tion: proprietary information page 119 register description control register file asynchronous transmit rambuffer 21 transmit rambuffer start address 0x0a80 sti transmit rambuffer end address 0x0a84 transmit buffer write pointer 0x0a88 transmit buffer read pointer 0x0a8c reserved 0x0a90 : 0x0a9c transmit rambuffer packet counter 0x0aa0 transmit rambuffer level 0x0aa4 transmit rambuffer control/test 0x0aa8 reserved 0x0aac : 0x0afc byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 120 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications receive mac fifo 24 reserved (legacy) 0x0c00 : 0x0c3c receive mac fifo end address 0x0c40 sti receive mac fifo almost full threshold 0x0c44 receive mac fifo control/test 0x0c48 receive mac fifo flush mask 0x0c4c receive mac fifo flush threshold 0x0c50 receive truncation threshold 0x0c54 reserved 0x0c58 receive vlan type register 0x0c5c receive mac fifo write pointer 0x0c60 reserved 0x0c64 receive mac fifo write level 0x0c68 reserved 0x0c6c receive mac fifo read pointer 0x0c70 reserved 0x0c74 receive mac fifo read level 0x0c78 reserved 0x0c7c reserved 25 reserved (legacy) 0x0c80 : 0x0cbc byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 121 register description control register file transmit mac fifo 26 reserved (legacy) 0x0d00 : 0x0d28 reserved 0x0d2c : 0x0d3c transmit mac fifo end address 0x0d40 sti transmit mac fifo almost empty threshold 0x0d44 transmit mac fifo control/test 0x0d48 reserved 0x0d4c : 0x0d58 transmit vlan type register 0x0d5c transmit mac fifo write pointer 0x0d60 transmit mac fifo write shadow pointer 0x0d64 transmit mac fifo write level 0x0d68 reserved 0x0d6c transmit mac fifo read pointer 0x0d70 transmit mac fifo restart pointer 0x0d74 transmit mac fifo read level 0x0d78 reserved 0x0d7c reserved 0x0d80 | 0x0dfc 27 byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 122 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications descriptor poll timer 28 timer init value 0x0e00 sti timer 0x0e04 reserved timer test reserved timer control 0x0e08 reserved 0x0e0c timestamp timer reserved 0x0e10 sti timer 0x0e14 reserved timer test reserved timer control 0x0e18 reserved 0x0e1c polling unit poll control 0x0e20 reserved list last index 0x0e24 list start address, low 0x0e28 list start address, high 0x0e2c reserved 0x0e30 : 0x0e3c reserved reserved reserved 0xe40 reserved 0xe44 reserved 0x0e48 : 0x0e5c reserved reserved 0xe60 reserved 0xe64 reserved 0xe68 byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 123 register description control register file host status and command register 0xe6c 28 data register 1 0xe70 data register 2 0xe74 data register 3 0xe78 data register 4 0xe7c byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 124 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications status bmu 29 status bmu control 0x0e80 reserved last index 0x0e84 list start address, low 0x0e88 list start address, high 0x0e8c reserved txa1 report index 0x0e90 reserved reserved 0x0e94 reserved tx index threshold 0x0e98 reserved put index 0x0e9c fifo control/status reserved fifo write pointer 0x0ea0 reserved fifo read pointer 0x0ea4 reserved fifo level 0x0ea8 reserved fifo isr watermark fifo watermark 0x0eac level timer level timer init value 0x0eb0 sti level timer counter 0x0eb4 reserved level timer test reserved level timer ctrl 0x0eb8 reserved 0x0ebc tx timer tx timer init value 0x0ec0 sti tx timer counter 0x0ec4 reserved tx timer test reserved tx timer control 0x0ec8 reserved 0x0ecc isr timer isr timer init value 0x0ed0 sti isr timer counter 0x0ed4 reserved isr timer test reserved isr timer ctrl 0x0ed8 reserved 0x0edc reserved 0x0ee0 0x0efc byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 125 register description control register file mac and phy control registers 30 reserved mac control 0x0f00 sti phy mux register phy control 0x0f04 reserved mac interrupt source 0x0f08 reserved mac interrupt mask 0x0f0c reserved link control 0x0f10 reserved 0x0f14 : 0xf1c wake on lan control registers match result match cont rol wol control/status 0x0f20 sti mac address low 0x0f24 reserved pme match enable mac address high 0x0f28 reserved pattern read pointer 0x0f2c pattern 3 length pattern 2 length pattern 1 length pattern 0 length 0x0f30 reserved pattern 6 length pattern 5 length pattern 4 length 0x0f34 pattern 3 counter pattern 2 counter p attern 1 counter pattern 0 counter 0x0f38 reserved pattern 6 counter pattern 5 counter pattern 4 counter 0x0f3c reserved 0x0f40 : 0xf7c reserved 0x0f80 : 0x0ffc 31 pattern ram 256 words x 32 bit 0x1000 : 0x13fc 32 : 39 pattern ram 256 words x 32 bit 0x1400 : 0x18fc 40 : 49 byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 126 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 0x1900 : 0x1984 50 : 51 reserved 0x1988 : 0x19fc reserved 0x1a00 : 0x1bfc 52 : 55 configuration register file 0x1c00 : 0x1e7c 56 : 60 reserved 0x1e80 : 0x1ffc 61 : 63 reserved reserved reserved (legacy) 0x2000 : 0x27fc 64 : 79 reserved reserved gmac register <0x00> (registers according to gmac datasheet) 0x2800 80 : 85 reserved reserved gmac register <0x01> 0x2804 reserved reserved gmac register <0x02> : gmac register <0x96> 0x2808 : 0x2a58 reserved reserved gmac register <0x97> 0x2a5c reserved 0x2a60 : 0x2afc reserved 0x2b00 : 0x2ffc 86 : 95 reserved reserved reserved (legacy) 0x3000 : 0x37fc 96 : 111 byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 127 register description control register file 3.3.2 registers 3.3.2.1 register address port (rap) address: 0x0000 width [bit]: 8 3.3.2.2 control/status register address: 0x0004 width [bit]: 24 reserved 0x3800 : 0x3ffc 112 : 127 bit name description write read reset (sw) register address port (rap) 31:7 reserved 6:0 rap specifies one out of blocks 0 to 127, which is mapped to the upper half of the 256 byte i/o range. 0: block 0 .. 0x7f: block 127 yes aw 0 bit name description write read reset control/status register status 23:18 reserved 17 vmain available vmain available is the vmain pin of the pci bus used as input with a weak pull- down. 0: no vmain available 1: vmain available ne value value byte<3> byte<2> byte<1> byte<0> address sti block marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 128 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 16 vaux available vaux available is the vaux pin of the pci bus used as input with a weak pull- down. 0: no vaux available 1: vaux available ne value value commands 15:14 reserved 13 reserved reserved exec 0b10 0 12 reserved 0b01 1 11:10 reserved exec 0b10 0 0b01 1 9 led<0>on led on/off commonly used as indication for ?driver loaded? exec 0b10 0 8 led<0> off 0b01 1 7 set irq sw sets and clears interrupt request from sw exec 0b10 0 6 clear irq sw 0b01 1 5 stop master done as soon as the master statemachine is in the idle state after stop master is set, stop master done is asserted. stop master done is reset to 0 by resetting stop master . ne value 0 4 stop master if stop master is set, all requests from the bmus except for the one being ser- viced at the moment, are masked. the master statemachine reaches the idle state after the current request is serviced. stop master has to be reset by the sw after the bmus are reset. if the bmus are not reset, the pci device resumes mas- ter action at the point, when it was inter- rupted by stop master . yes aw 0 (hw) 3 master reset clear set/clear master reset. if master reset is set, all devices related to the master interface (bmus, fifos, state machines) are in their reset state. executed, if appropriate bit is set to 1. exec 0b10 0 2 master reset set 0b01 1 (sw) bit name description write read reset marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 129 register description control register file 3.3.2.3 power control register address: 0x0007 width [bit]: 8 1 sw reset clear set/clear sw reset. executed, if appropriate bit is set to 1. if sw reset is set, all internal and exter- nal devices are in their reset state. exec 0b10 0 0 sw reset set 0b01 1 (hw) bit name description write read reset (power on) power control register 7 switch vaux enable switch vaux enable 1 = output switch vaux pin enabled 0 = output switch vaux pin disabled exec 0b10 0 6 switch vaux dis- able 0b01 1 5 switch vcc enable switch vcc enable 1 = output switch vcc pin enabled 0 = output switch vcc pin disabled exec 0b10 0 4 switch vcc disable 0b01 1 3 switch vaux on switch vaux on/off 1 = power supply from vaux pin on 0 = power supply from vaux pin off exec 0b10 0 2 switch vaux off 0b01 1 1 switch vcc on switch vcc on/off 1 = power supply from vcc pins on 0 = power supply from vcc pins off exec 0b10 0 0 switch vcc off 0b01 1 bit name description write read reset marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 130 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.4 interrupt source register address: 0x0008 width [bit]: 32 if set to one, interrupt is pending bit name description write read reset (sw) interrupt source register general interrupts 31 hw interrupt 1: at least one of the hw interrupts oc- curred ( interrupt hw error source register ), which is not masked by the according mask register. 0: no hw interrupt active ne value 0 30 status bmu interrupt on status burst ne value 0 29 reserved reserved ne value 0 28 reserved 27 irq polling chk check interrupt by the polling unit ne value 0 26 irq twsi ready interrupt on completion of twsi transfer ne value 0 25 irq sw interrupt set by sw in control register ne value 0 24 irq timer interrupt timer ne value 0 23:16 reserved interrupts 7:5 reserved 4 irq phy interrupt from phy ne value 0 3 irq mac interrupt from mac ne value 0 2 irq chck rx interrupt coding e rror of descriptor (rx queue) ne value 0 1 reserved ne value 0 0 irq chck txa interrupt coding e rror of descriptor (asynchronous tx queue) ne value 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 131 register description control register file 3.3.2.5 interrupt mask register address: 0x000c width [bit]: 32 each bit position defines, if the dedicated interr upt is propagated to the internal interrupt line irq . the enable bits have the same bit positions as in the interrupt source register. unused bit positions are treated like reserved. if set to one, interrupt is enabled. see also ? special interrupt source register ?. 3.3.2.6 interrupt hw error source register address: 0x0010 width [bit]: 32 bit name description write read reset (sw) interrupt mask register 31:0 en irq xxx enable interrupt xxx yes aw 0 bit name description write read reset (sw) interrupt hw error source register general interrupts 31:30 reserved 29 irq timestamp timer overflow interrupt timestamp timer overflow ne value 0 28 irq sensor interrupt from sensor this external interrupt line is connected to the interrupt output of the voltage/tem- perature sensor ne value 0 27 irq master error interrupt master error detected on mas- ter accesses set, if dataperr , rtabort or rm- abort are set. ne value 0 26 irq status interrupt status exception set, if perr, rmabort, rtabort or dataperr are set. ne value 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 132 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.7 interrupt hw error mask register address: 0x0014 width [bit]: 32 each bit position defines, if the dedicated interrupt is propagated to the interrupt line inta# . the enable bits have the same bit positions as in the interrupt hw error source register. unused bit positions are treated like reserved. bits, which are dedicated to a potential second ma c are reserved, but their setting have no effect. if set to one, interrupt is enabled. 25 irq pe pci express interrupt indication of occurrence of uncorrectable error(s) in pci-express mode ne value 0 24 irq no pe an error occurs in pci-express mode. note: this is not a pci-express error! ne value 0 23:16 reserved hw interrupts 7:6 reserved 3 irq par mac interrupt parity error/mac this interrupt is intended to indicate a panic event (hardware fault) ne value 0 2 irq par rx interrupt parity error (rxqueue ) this interrupt is intended to indicate a panic event (hardware fault) ne value 0 1 ne value 0 0 irq tcp length txa1 interrupt length mi smatch (asynchro- nous tx queue 1) with tcp segmenta- tion ne value 0 bit name description write read reset (sw) interrupt hardware error mask register 31:0 en irq xxx enable hardware interrupt xxx yes aw 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 133 register description control register file 3.3.2.8 special interr upt source register 1 address: 0x0018 width [bit]: 32 this register mirrors the interrupt source register with special functionality adapted to typical sw handling. if the internal interrupt line irq is asserted, the read value is the same as in the interrupt source register . if the internal interrupt line irq is not asserted, the read value is 0. if the internal interrupt line irq is asserted, reading the special interrupt source register 1 masks all interrupts. as a result the internal interrupt line irq is deasserted. bit positions are the same as in the interrupt source register. 3.3.2.9 special interr upt source register 2 address: 0x001c width [bit]: 32 this register mirrors the interrupt source register with special functionality adapted to typical sw handling. if the internal interrupt line irq is asserted, the read value is the same as in the interrupt source register . if the internal interrupt line irq is not asserted, the read value is 0. if the internal interrupt line irq is asserted, reading the special interrupt source register 2 masks all interrupts and sets isr status flag of interrupt control register to ?isr mode?. as a result the internal interrupt line irq is deasserted. bit positions are the same as in the interrupt source register. bit name description write read reset (sw) special interrupt source register 1 31:0 irq xxx interrupt xxx when the internal interrupt line irq is as- serted, read masks all interrupts. as a re- sult the internal interrupt line irq is deasserted. ne value or 0 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 134 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.10 special interr upt source register 3 address: 0x0020 width [bit]: 32 this register mirrors the interrupt source register with special functionality adapted to typical sw handling. if the internal interrupt line irq is asserted, the read value is the same as in the interrupt source register . if the internal interrupt line irq is not asserted, the read value is 0. reading the special interrupt source register 3 always masks all interrupts. as a re sult the internal interrupt line irq is deasserted. if the internal interrupt line irq is asserted, isr_status flag is set to ?isr mode?. bit positions are the same as in the interrupt source register. bit name description write read reset (sw) special interrupt source register 2 31:0 irq xxx interrupt xxx when the internal interrupt line irq is as- serted, read masks all interrupts. as a re- sult the internal interrupt line irq is deasserted. when irq is active, the isr status flag of interrupt control register is set to ?isr mode?. ne value or 0 0 bit name description write read reset (sw) special interrupt source register 3 31:0 irq xxx interrupt xxx read masks all interrupts. as a result the internal interrupt line irq is deasserted. when irq is active, the irq status flag is set to ?isr mode?. ne value or 0 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 135 register description control register file 3.3.2.11 enter interrupt service routine register address: 0x0024 width [bit]: 32 3.3.2.12 leave interrupt service routine register address: 0x0028 width [bit]: 32 bit name description write read reset (sw) enter interrupt service routine register 31:0 enter isr reg read: isr_status is set and all interrupts are masked. value of interrupt source register is re- turned write: no effect ne value 0 bit name description write read reset (sw) leave interrupt service routine register 31:0 leave isr reg read: isr_status is reset and the overall masking of interrupts is released. value of interrupt source register is re- turned write: no effect ne value 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 136 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.13 interrupt control register address: 0x002c width [bit]: 32 3.3.2.14 spi flash memory control register address: 0x0060 width [bit]: 32 bit name description write read reset (sw) interrupt cont rol register 31:4 reserved ne 0 0 3 isr_mask isr_mask flag value ne value 0 2 isr_status isr_status flag value 1: ?isr mode? 0: ?normal mode? ne value 0 1 leave isr written to with 1: isr_status is reset and the overall masking of interrupts is re- leased. exec 0 0 0 enter isr written to with 1: isr_status is set and all interrupts are masked. exec 0 0 bit name description write read reset (hw) spi flash memory control register 31 loader start start to load spi configuration from load- er start address, software can reload again using this bit. start to load spi con- figuration from the current address stored in the spi flash memory address regis- ter. during the loading time software access- es to registers are hold until loading has been finished. yes 0 0 30 spi busy status bit indicating that a command is in progress on the spi no yes 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 137 register description control register file 29 spi vpd enable 0: (default) vpd provided in twsi ee- prom 1: vpd is mapped to spi flash memo- ry. enables vpd accesses to the spi flash memory. yes yes 0 28 rd id protocol spi flash memories of different vendors need different protocols for reading the id: 0: the id is transferred immediately by the spi flash memory after read id instruction is initiated (atmel flash memory). 1: dummy address write (3 zero bytes) should precede the initial read id instruction. (sst and st spi flash memories) yes aw 0 27:20 reserved yes 0 0 19 start spi an spi instruction is initiated by writing a ?1? to this register bit. exec 0 0 18:16 instruction selection of one of the opcodes of the spi flash memory opcode registers: 0: opcode no operation 1: opcode read 2: opcode read id 3: opcode read status register 4: opcode write enable 5: opcode write 6: opcode sector erase 7: opcode chip erase yes yes 0 15:8 reserved yes 0 0 7:0 spi device status contents of the status register from the spi device. register is updated only after executing the read status register command by the spi flash memory. during write access or erasing of spi flash memory, software should continue initiate read status register instruction and afterwards reading this register until the last bit- bit[0] is 0 before start of next write or read access. no yes 0x00 bit name description write read reset (hw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 138 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.15 spi flash memory address register address: 0x0064 width [bit]: 32 3.3.2.16 spi flash memory data register address: 0x0068 width [bit]: 32 3.3.2.17 spi flash memory vendor/device id register address: 0x006c width [bit]: 32 bit name description write read reset (hw) spi flash memory address register 31:20 reserved yes 0 0 19:0 spi flash mem- ory address spi flash memory address for read or write accesses to the spi flash memory yes yes 0x0000 0 bit name description write read reset (hw) spi flash memory data register 31:0 spi flash mem- ory data spi flash memory data for write access- es or result of read access to the spi flash memory yes yes 0x0000 0 bit name description write read reset (hw) spi flash memory vendor/device id register 31:16 reserved yes 0 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 139 register description control register file 3.3.2.18 spi flash memory loa der configuration register address: 0x0070 width [bit]: 32 15:8 vendor-id to identify the vendor of the flash each device has a special code which can be read out with the rdid instruction no yes 0x00 7:0 device-id to identify the flash device each device has a special code which can be read out with the rdid instruction no yes 0x00 bit name description write read reset (hw) spi flash memory loader configuration register 31:28 reserved yes 0 0 27:16 normal loader start address start address of configuration data with- in spi flash memory after reset spi flash memory loader starts to load configuration data from this address. address is aligned to 256 byte bound- aries. these bits are the higher bits of the address and bits 7:0 are set to ?0? implicit- ly. yes yes 0x1f8 15:12 reserved yes 0 0 11:0 pig loader start address start address of configuration data with- in spi flash memory when in plug-in-go mode during power save mode spi flash memory loader will start to load configu- ration data from this address address is aligned to 256 byte bound- aries. these bits are the higher bits of the address and bits 7:0 are set to ?0? implicit- ly. yes yes 0x1f0 bit name description write read reset (hw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 140 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.19 spi flash memory vpd configuration register address: 0x0074 width [bit]: 32 3.3.2.20 spi flash memory opcode 1 and 2 register address: 0x0078, 0x007c width [bit]: 2 x 32 the listed default values for the opcodes are valid for sst?s serial flash memories. the values must be adapted by software when using spi fl ash memories of other prov iders. especially the op- codes of sector erase, chip erase and read id must be changed. all other opcodes are equal for the spi flash memories supported by yukon? ec. bit name description write read reset (hw) spi flash memory vpd configuration register 31:28 reserved yes 0 0 27:16 vpd end address when vpd is mapped into spi flash memory, vpd area ends at this address. accesses beyond this end address are invalid accesses. address is aligned to 256 byte bound- aries. these bits are the higher bits of the address and bits 7:0 are set to ?0? implic- itely. yes yes 0x1c1 15:12 reserved yes 0 0 11:0 vpd start address when vpd is mapped into spi flash memory, vpd area starts at this address. accesses below this start address are in- valid accesses. address is aligned to 256 byte bound- aries. these bits are the higher bits of the address and bits 7:0 are set to ?0? implic- itely. yes yes 0x1c0 bit name description write read reset (hw) spi flash memory opcode 1 register marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 141 register description control register file 31:24 opcode read status opcode for reading the status register of spi flash memory. result is stored with- in lower bits of spi flash memory control register. yes aw 0 23:16 opcode read id opcode for reading the vendor/ device id out of spi flash memory. result is stored within spi flash memory vendor/ device id register. yes aw 0 15:8 opcode read opcode for read data out of spi flash memory at address of spi flash memory address register. result is stored within spi flash memory data register. yes aw 0 7:0 opcode no oper- ation opcode for no operation yes aw 0 spi flash memory opcode 2 register 31:24 opcode chip erase opcode for spi flash memory chip- erase command. during execution of this operation software should check spi de- vice status bit[0], spi has not finished erasing until status bit[0] is 0. yes aw 0 23:16 opcode sector erase opcode for a spi flash memory sector- erase command. during execution of this operation software should check spi de- vice status bit[0], spi has not finished erasing until status bit[0] is 0. yes aw 0 15:8 opcode write opcode for writing data of spi flash memory data register into spi flash memory at address of spi flash memory address register. yes aw 0 7:0 opcode write enable opcode for the wren command which sets the write enable latch. after execu- tion of this command a sector erase, chip erase or program command should follow. yes 0 0 bit name description write read reset (hw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 142 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.21 block window address: 0x0080.. 0x00fc width [bit]: 128 x 32 one block of the control register file is mapped in to this address space according to the setting of register ad- dress port . when the contents of the register address port is one (rap = 1) this block window is mapped to itself. all read values are zero and write cycles have no effect. 3.3.2.22 mac-address regist ers link and maintenance address: 0x0100 width [bit]: 6 x 8 (link) address: 0x0110 width [bit]: 6 x 8 (maintenance) these registers hold the mac address. mac addr_x: x maybe 1 or 3 for the two implemented link (1) and maintenance (3). they are loaded at power on reset from the spi flash memory or twsi eeprom. they may be written in testmode. bit name description write read reset (hw) mac-address registers 31:16 reserved 15:8 mac addr_x<5> mac-address, byte 5 ne value 0 7:0 mac addr_x<4> mac-address, byte 4 ne value 0 31:24 mac addr_x<3> mac-address, byte 3 ne value 0 23:16 mac addr_x<2> mac-address, byte 2 ne value 0 15:8 mac addr_x<1> mac-address, byte 1 ne value 0 7:0 mac addr_x<0> mac-address, byte 0 ne value 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 143 register description control register file 3.3.2.23 interface type register (pmd type and connector type) address: 0x0118 width [bit]: 16 this register holds the type of interface. it is loaded at power on reset from the spi flash memory or the twsi eeprom. it may be written in testmode. 3.3.2.24 chip revision register address: 0x011a width [bit]: 8 this register holds chip revision number. the chip revision is fixed to th e current chip revision number. bit name description write read reset (hw) interface type register 15:8 pmd pmd type ne value 0 7:0 connector connector type ne value 0 bit name description write read reset (hw) chip revision register 7:4 chip revision initial revision is 0x0 fixed value (incremented with chip revi- sion) ne 00 revision 3:0 reserved ne value value marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 144 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.25 chip id register address: 0x011b width [bit]: 8 this register holds the chip identification code. 3.3.2.26 spi flash memory registers address: 0x011c width [bit]: 4 x 8 these registers hold optional information. they are loaded at power on reset from the spi flash memory. they are loaded at power on reset from the spi flash memory. they may be written in testmode (besides ram size field and bond status bits). bit name description write read reset (hw) chip id register 7:0 chip id initial id is 0xb6 fixed value ne 0xb6 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 145 register description control register file bit name description write read reset (hw) eprom registers 31:24 eprom<3> eprom, byte 3 ne value 0 eprom<2> hw resources 23:17 reserved ne value 0 16 link available 0: link not available (not implemented in device) 1: link available ne value 0 eprom<1> clock gating 15:12 reserved ne value value 11 bond_status link status of input signal (pin strapping): 0: link active 1: link inactive ne value value 10 disable phy/mac link clock gating for ref_clk/mac_clk for link 0: clock enabled for link 1: clock disabled ne value 0 9 disable core_clk link clock gating for core_clk for link 0: clock enabled for link 1: clock disabled ne value 0 8 disable pci_clk link clock gating for pci_clk for link 0: clock enabled for link 1: clock disabled ne value 0 eprom<0> ram size 7:0 eprom<0> ram size eprom, byte 0 ram size specification: 0x0c: 12 x 4 kb = 48 kb (fixed value) ne 0x0c marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 146 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.27 clock divider register address: 0x0120 width [bit]: 32 3.3.2.28 irq timer registers address: 0x0130 width [bit]: 3 x 32 usage of the timer is described in chapter 3.23 timer on page 278. bit name description write read reset (sw) clock division value yes aw 0 31:24 23:16 clock div value selection of divisor for clock division of core clock: 0: divide clock by 2 1: divide clock by 4 : n: divide clock by (n+1)*2 : 255:divide clock by 512 minimum core clock frequency is 0.241 mhz (125 mhz/512) yes value 3 clock division control 15:2 reserved 1 clock div enable enable/disable clock division of core clock for power saving purposes default: disabled 0b01 exec 0b10 0 0 clock div disable 0b01 1 bit name description write read reset (sw) 31:0 timer init value yes aw 0 31:0 timer yes (for tests only) value 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 147 register description control register file the timer implements write posting and retries the follo wing accesses to the timer while a posted write is in progress. target reads are retried until the addresse d register is synchronized to pci clock. 3.3.2.29 irq moderati on timer registers address: 0x0140 width [bit]: 3 x 32 usage of the irq moderation timer is described in chapter 3.13 interrupts on page 223. timer control/test 31:16 reserved te s t 15:11 reserved 10 timer test on testmode on/off exec 0b10 0 9 timer test off 0b01 1 8 timer step timer decrement exec 0 control 7:3 reserved 2 timer start start/stop timer exec 0b10 0 1 timer stop 0b01 1 0 timer clear irq clear timer interrupt exec 0 bit name description write read reset (sw) 31:0 irq moderation timer init value yes aw 0 31:0 irq moderation timer yes value 0 irq moderation timer control/test 31:16 reserved te s t 15:11 reserved 10 im timer test on testmode on/off exec 0b10 0 9 im timer test off 0b01 1 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 148 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications the irq moderation timer implements write posting an d retries the following accesses to the irq moderation timer while a posted write is in progress. target reads are retried until the addressed register is synchronized to pci clock. 3.3.2.30 interrupt moderation mask register address: 0x014c width [bit]: 32 each bit position defines, if the dedicated interrupt is moderated or propagated directly to the interrupt line inta# . the enable bits have the same bit positions as in the interrupt source register. unused bits are treated like re- served. if set to one, interrupt is moderated. if set to zero, interrupt is propagat ed directly to the interrupt line inta#. the interrupts of the mac interrupt source register cannot be moderated separately. 8 im timer step timer decrement exec 0 control 7:3 reserved 2 im timer start start/stop im timer exec 0b10 0 1 im timer stop 0b01 1 0 reserved bit name description write read reset (sw) interrupt moderati on mask register 31:0 en mod irq xxx enable moderation interrupt xxx yes aw 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 149 register description control register file 3.3.2.31 interrupt hardware error moderation mask register address: 0x0150 width [bit]: 32 each bit position defines, if the dedic ated interrupt is moderated or propaga ted directly to the interrupt line inta# . the enable bits have the same bit positions as in the interrupt hw error source register. unused bits are treat- ed like reserved. if set to one, interrupt is moderated. if set to zero, interrupt is propaga ted directly to the interrupt line inta#. 3.3.2.32 general purpose io register address: 0x015c width [bit]: 32 for further extension the general purp ose io pins are routed to the general purpose registers. these ios are programmable as inputs or outputs bit name description write read reset (sw) interrupt hardware error moderation mask register 31:0 en mod irq xxx enable moderation hardware interrupt xxx yes aw 0 bit name description write read reset value 31 clock debug enable 0 = disable clock debug 1 = enable clock debug selected clock will be muxed out to vpd_clk pin. yes aw 0 30 reserved 29:26 clk debug 0000 = pci_clk 0001 = clk_pci 0010 = clk25 0111 = spi_clk 1001 = clk_core 1010 = smclk_in 1100 = pipe_clk yes aw 0 25:16 gpio dir<9:0> defines the type of the general purpose io pins. 1=output 0 = input in this application only gpio<3:0>are avail- able as external pins yes aw 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 150 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.33 twsi (hw) registers address: 0x0160 width [bit]: 3 x 32 15:11 reserved 10 random number random number serializer enable 9 reserved reserved 8:0 gpio<8:0> these bits are routed to the asic?s pins for future external options. as output they are synchronous to pci clock, as input they are synchronized to pci clo ck. in this applica- tion only gpio<3:0>are available as exter- nal pins yes aw 0 bit name description write read reset value twsi (hw) control register (address: 0x0160, width 32) 31 flag starts the twsi data transfers, determines its direction and signals its completion by being toggled by hw. if written 1, a twsi write is started. set to 0 after completion. if written 0, a twsi read is started. set to 1 after completion. generates an interrupt on completion. exec value 0 30:16 twsi address address of the twsi device register to be written/read. yes aw 0x00 15:9 twsi devsel devsel byte of the twsi device to be writ- ten/read. yes aw 0x00 8:5 reserved 4 twsi burst 0 = single byte transfers 1 = 4 byte page mode write transfers with fixed page size of 8 bytes assumed yes aw 0 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 151 register description control register file these registers implement a serial twsi interface to the optional temperature/voltage sensor. hw runs the 100 khz serial twsi protocol to obtain data. the hw controlled twsi interface and the sw controlle d twsi interface are connected to the same twsi bus (pins twsi_data and twsi_clock). they must not be used in parallel. if the hw controlled twsi interface is used, the twsi (sw) register has to be set to inactive values (reset val- ues). if the sw controlled twsi interfac e is used, the hw controlled twsi interface must not be started ( flag/ twsi (hw) register). the twsi clock and data port pins are pulled high by a pull up resistor to vcc of the twsi device. 3:1 twsi device size defines the size of the addressed twsi de- vice in bytes. 0: 256 bytes and smaller 1: 512 bytes 2: 1024 bytes 3: 2048 bytes 4: 4096 bytes 5: 8192 bytes 6: 16384 bytes 7: 32768 bytes default value is 256 bytes. yes aw 0x00 0 twsi stop a written 1 interrupts the current twsi transfer at the next byte boundary with a stop condition and signals end of twsi transfer by toggling flag . exec 0 0 twsi (hw) data register (address: 0x0164, width 32) 31:0 twsi data must be written before twsi address reg- ister for twsi write. contains twsi read data after completi on of twsi read. yes aw 0x00 twsi (hw) irq register (address: 0x0168, width 32) 31:1 reserved 0 clear irq twsi clears interrupt request from twsi hw in- terface exec aw 0 bit name description write read reset value marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 152 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.34 twsi (sw) register address: 0x016c width [bit]: 32 this register implements a serial twsi interface to the optional temperature/voltage sensor. sw has to run the se- rial twsi protocol to obtain data. as output, the data port must simulate an open collector output in order to obtain a 0.7 vcc signal level at the twsi device (if supplied with 5 v). driving to low level: twsi data = 0 twsi data dir =1 floating to high level: twsi data = x twsi data dir =0 the hw controlled twsi interface and the sw controlled twsi interface are connected to the same twsi bus (pins twsi_data and twsi_clock). they must not be used in parallel. if the hw controlled twsi interface is used, the twsi (sw) register has to be set to inactive values (reset val- ues). if the sw controlled twsi interface is used, the hw controlled twsi interface must not be started ( flag/ twsi (hw) register). the twsi clock and data port pins are pulled high by a pull up resistor to vcc of the twsi device. bit name description write read reset (sw) twsi (sw) register 31:3 reserved 2 twsi data dir defines direction of twsi data port: 0 = input 1=output yes aw 0 1 twsi data twsi interface data port yes dir=0: value dir=1: aw 0 0 twsi clock twsi interface clock yes aw 1 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 153 register description control register file 3.3.2.35 pex phy address/data registers address: 0x0170 width [bit]: 32 the phys of the pci express part are ma de accessible via the following registers. 3.3.2.36 ram random registers address: 0x0180 - 0x0188 width [bit]: 3 x 32 bit name description write read reset (sw) pex phy address register 31 pex phy access mode 0: write access to pex phy register 1: read pex phy register and store data into data region bits 15:0 of this register. yes aw 0 30 pex phy regfile 0: phy?s register file of pex module 1: pex debug register file yes aw 0 29:16 pex phy address 14 bit phy/debug address for pci ex- press module yes aw 0 pex phy data register 15:0 pex phy data 16 bit phy data for pci express module yes aw 0 bit name description write read reset (sw) ram address (offset: 0x00, width: 32) 31:19 reserved 18:0 ram address defines ram address in qwords. yes aw 0 data port/lower dword (offset: 0x04, width: 32) 31:0 data port/lower dword dataport/lower dword for exchange of read/write data. on a pci read access, reading from ram to the data ports is initiated. the initiating pci access and subse- quent accesses are retried on pci while reading from ram yes value exec 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 154 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.37 ram inte rface registers address: 0x0190 - 0x01a0 width [bit]: 5 x 32 the timeout values limit the burst length of data transfers for each requestor individually. default values must be used. data port/upper dword (offset: 0x08, width: 32) 31:0 data port/upper dword dataport/upper dword for exchange of read/write data. on a pci write access, writing to ram from the data ports is initiated. subsequent pci accesses are retried on pci while writing to ram yes exec value 0 bit name description write read reset (pri- vate) timeout init values 0 - 3 (offset: 0x00, width: 32) 31:24 timeout init value 3 read sm rx1 yes aw 32 23:16 reserved write sm txs1 yes aw 32 15:8 timeout init value 1 write sm txa yes aw 32 7:0 timeout init value 0 write sm rx yes aw 32 timeout init values 4 and 5 (offset: 0x04, width: 32) 31:16 reserved (leg- acy) 15:8 reserved yes aw 32 7:0 timeout init value 4 read sm txa yes aw 32 31:0 reserved bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 155 register description control register file timeout timer (offset: 0x0c, width: 32) 31:8 reserved 7:0 timeout timer yes (for tests only) value 0 ram interface control/test (offset: 0x10, width: 32) te s t 31:20 reserved 19 timeout 1: if timeout timer = 0 ne value 1 18 timeout timer test on testmode on/off exec 0b10 0 17 timeout timer test off 0b01 1 16 timeout timer step timer decrement exec 0 control 15:10 reserved 9 clear irq par rd ram clear parity error on read interrupt exec 0 8 clear irq par wr ram clear parity error on write interrupt exec 0 7:2 reserved 1 reset clear set/clear reset. executed, if appropriate bit is set to 1. if reset is set, all ram interface func- tions and registers are in their reset state. reset is forwarded to the ram random access device in order to avoid a hangup on a target access while the ram interface is reset. exec 0b10 0 0 reset set 0b01 1 (sw) bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 156 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.38 transmit arbiter registers address: 0x0200 - 0x0210 width [bit]: 5 x 32 bit name description write read reset (sw) interval timer init value (offset: 0x00, width: 32) 31:0 interval timer init value number of core clock cycles as time in- terval for rate control. t max = 27.53 s yes aw 0 interval timer (offset: 0x04, width: 32) 31:0 interval timer interval timer value: number of core clock cycles (125 mhz) t max = 27.53 s yes aw 0 limit counter init value (offset: 0x08, width: 32) 31:24 reserved 23:0 reserved yes aw 0 limit counter (offset: 0x0c, width: 32) 31:0 limit counter yes aw 0 timer/counter control/status/test (offset: 0x10, width: 32) status 31:17 reserved 16 priority/sync. rambuffer set as long limit counter not zero or if force sync on is set ne value 0 te s t 15:14 reserved 13 interval timer test on testmode on/off exec 0b10 0 12 interval timer test off 0b01 1 11 interval timer step timer decrement exec 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 157 register description control register file 3.3.2.39 rss key registers address: 0x0220 - 0x022c width [bit]: 4 x 32 address: 0x02a0 - 0x02ac width [bit]: 4 x 32 rss is described in ?receive-side scaling hash design specification? by microsoft corporation. 10 limit counter test on testmode on/off exec 0b10 0 9 limit counter test off 0b01 1 8 limit counter step counter decrement exec 0 control 6 force sync off 0b01 1 4 dis alloc 0b01 1 2 rate ctrl stop 0b01 1 1 arbiter opera- tional on operational mode on/off if off, no request is granted. has to be set to off until all other devic- es are initialized exec 0b10 0 0 arbiter opera- tional off 0b01 1 bit name description write read reset (sw) rss key 0 (offset: 0x00, width: 32) 31:0 rss key 0 part 0 (lsb) of random key for rss hash algorithm yes aw 0 rss key 1 (offset: 0x04, width: 32) 31:0 rss key 1 part 1 of random key for rss hash algo- rithm yes aw 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 158 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.40 pci configuration registers address: 0x0380 - 0x03fc width [bit]: 32 x 32 the configuration register file is mapped add itionally into the control register file. at this place the lower 128 bytes of the configuration register files are mapped. the whole configuration regis- ter file is mapped to blocks 56 up to 60. it is read only with some exceptions: our register 1 and 2 and vpd address and vpd data register may be written. write operations are completed normally on the bus and the data is discarded. for testing purposes, the configuration register file may be set writable by en config write . 3.3.2.41 bmu registers for receive queues address: 0x0400 - 0x044c width [bit]: 20 x 32 (receive queue , structure as shown below) these registers are intended to be used for testing and diagnostic purposes, except the control/status regis- ters and watermark for initialization. manipulating the content of these registers under ?nor mal? running conditions is not recommended and may lead to undefined results. if the default values are acceptable, the watermark should not be written (for future backward compatibility, if wa- termarks/fifo depth are adapted). for each receive queue in each link a separate set of registers is implemented. rss key 2 (offset: 0x08, width: 32) 31:0 rss key 2 part 2 of random key for rss hash algo- rithm yes aw 0 rss key 3 (offset: 0x0c, width: 32) 31:0 rss key 3 part 3 (msb) of random key for rss hash algorithm yes aw 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 159 register description control register file bit name description write read reset (sw) receive queue registers current receive descriptor (offset: 0x00, width: 2 x 16) 31:16 receive buffer control highest 16 bit of current list element (when of type buffer) own bit, opcode, control bits to value 0 15:0 receive buffer byte count to value 0 rss hash checksum (offset: 0x04, width: 32) 31:0 rss hash check- sum result of rss hash calculation, when enabled. receive buffer address (offset: 0x08, width: 2 x 32) 31:0 receive buffer address lo lower part of receive buffer address to value 0 31:0 receive buffer address hi higher part of receive buffer address to value 0 receive buffer status word (offset: 0x10, width: 32) 31:0 rfsw receive frame status word as defined by gmac (including length). valid, if own is cleared by the bmu and eof is set. if not valid, the bmu writes back, what received at that place. to value 0 receive timestamp (offset: 0x14, width: 32) 31:0 timestamp receive timestamp as defined by the timestamp timer at writing the receive status word to the receive mac fifo. valid, if own is cleared by the bmu and eof is set. if not valid, the bmu writes back, what received at that place. to value 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 160 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications tcp/ip checksum extension (offset: 0x18, width: 4 x 16) the list element tcppar containing the start addresses of the two checksums enables tcp /ip checksum calculation. tcp/ip checksums 1 & 2 (16 bit) are calculated from tcp sum start 1 & 2 up to the end of the packet. the checksums are written to tcp sum 1 & 2. the byte order within the tcp sum is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). note: an fcs appended to the frame by the gmac is also add- ed to the checksum. if the calculation does not end 16-bit-aligned at the end of the packet, the missing byte is seen as 0. registers holding these values are updated only, if stf is set (except tcp sum 1 & 2 ) 31:16 checksum 2 checksum 2 valid, if own is cleared by the bmu and eof is set. defined by the pci device, if eof is set to value 0 15:0 checksum 1 checksum 1 valid, if own is cleared by the bmu and eof is set. defined by the pci device, if eof is set to value 0 31:16 start position 2 checksum 2, start posit ion for calculation in bytes (16-bit aligned) counted from zero (first byte = 0) defined by the host, if stf is set to value 0 15:0 start position 1 checksum 1, start posit ion for calculation in bytes (16-bit aligned) counted from zero (first byte = 0) defined by the host, if stf is set to value 0 vlan tag (offset: 0x20, width: 16) 31:16 reserved to value 0 15:0 vlan tag received vlan tag bytes out of data stream the byte order within the vlan tag val- ue is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 161 register description control register file done index (offset: 0x24, width: 16) 31:12 reserved 11:0 done index incremented for each processed list ele- ment to value 0 request address (offset: 0x28, width: 2 x 32) 31:0 request addr lo lower 32 bit of current request address to value 0 31:0 request addr hi higher 32 bit of current request address to value 0 request byte count (offset: 0x30, width: 16) 31:11 reserved 10:0 request byte count length of current request in number of bytes to value 0 bmu control/status register (offset: 0x34, width: 32) 31 bmu idle status bit bmu in idle state ne value 1 30 tcp pkt flag: ?1?, if current packet is tcp/ip only valid, when rss hash enabled to value 0 29 ip pkt flag: ?1?, if current packet is ip only valid, when rss hash enabled to value 0 28:16 reserved 15 rss hash enable enables/disables rss hash calculation for receive queue default: disabled (0b01) exec 0b10 0 14 rss hash dis- able 0b01 1 13 rx checksum enable enables/disables tcp/ip checksum check default: disabled (0b01) exec 0b10 0 12 rx checksum disable 0b01 1 11 clear irq parity clear irq on parity errors (rx bmu fifo read data parity error) exec 0 0 10 clear irq check clear irq check. (this interrupt is asserted when receiving a wrong opcode within a list element) exec 0 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 162 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 9 stop rx bmu 10: stop receive queue transfer after next end of packet 01: normal operation (default) exec 0b10 0 8 start rx bmu 0b01 1 7 fifo operational on default: off (0b01) must be switched to on after initialization exec 0b10 0 6 fifo operational off 0b01 1 5 fifo enable default: reset (0b01) exec 0b10 0 4 fifo reset 0b01 1 3 bmu operational on default: off (0b01) must be switched to on after initialization exec 0b10 0 2 bmu operational off 0b01 1 1 bmu enable default: reset (0b01) exec 0b10 0 0 bmu reset 0b01 1 bmu test register (offset: 0x38, width: 32) 31:23 reserved 22 testmode shad- ow read ptr on switch to testmode shadow read point- er default: operation (testmode = off) exec 0b10 0 21 testmode shad- ow read ptr off 0b01 1 20 teststep shadow read ptr teststep: increment shadow read point- er exec 0 0 19 reserved 18 testmode read ptr on switch to testmode read pointer default: operation (testmode = off) exec 0b10 0 17 testmode read ptr off 0b01 1 16 teststep read ptr teststep: increment read pointer exec 0 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 163 register description control register file 15 reserved 14 testmode shad- ow write ptr on switch to testmode shadow write point- er default: operation (testmode = off) exec 0b10 0 13 testmode shad- ow write ptr off 0b01 1 12 teststep shadow write ptr teststep: increment shadow write point- er exec 0 0 11 reserved 10 testmode write ptr on switch to testmode write pointer default: operation (testmode = off) exec 0b10 0 9 testmode write ptr off 0b01 1 8 teststep write ptr teststep: increment write pointer exec 0 0 7 reserved 6 testmode req nbytes/addr on switch to testmode request nbytes/ad- dresses default: operation (testmode = off) exec 0b10 0 5 testmode req nbytes/addr off 0b01 1 4 teststep req nbytes/addr teststep request nbytes/addresses an acknowledge from biu is emulated and as a result address counter is incre- mented by nbytes and nbytes is reset to zero. exec 0 0 3 reserved 2 testmode done index on switch to testmode done index default: operation (testmode = off) exec 0b10 0 1 testmode done index off 0b01 1 0 teststep done in- dex teststep: increment done index exec 0 0 bmu statemachine register (offset: 0x3c, width: 32) 31:0 state variables of all statemachines (writable only, when in operational mode, but then remains not the written value) to value 0x00 (idle state) bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 164 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications fifo watermark (offset: 0x40, width: 16) 15:11 reserved 10:0 fifo watermark (bytes) yes tbd: ito? aw 0x600 fifo alignment (offset: 0x42, width: 8) 15:7 reserved 6:4 mux multiplexer setting ne value 0 3 reserved 2:0 vram vram position yes value 0 fifo read shadow pointer (offset: 0x44, width: 16) 15:11 reserved 10:0 fifo read shadow pointer (bytes) to value 0 fifo read shadow level (offset: 0x46, width: 8) 15:8 reserved 7:0 fifo read shadow level (qword) ne value 0 fifo read pointer (offset: 0x48, width: 8) 15:8 reserved 7:0 fifo read pointer (qword) to value 0 fifo read level (offset: 0x4a, width: 8) 15:8 reserved 7:0 fifo read level (qword) ne value 0 fifo write pointer (offset: 0x4c, width: 8) 7:0 fifo write pointer (qword) to value 0 fifo write shadow pointer (offset: 0x4d, width: 8) 7:0 fifo write shadow pointer (qword) to value 0 fifo write level (offset: 0x4e, width: 8) 7:0 fifo write level (qword) ne value 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 165 register description control register file 3.3.2.42 bmu registers for transmit queues address: 0x0680 - 0x06cc width [bit]: 20 x 32 (asynchronous transmit queue) these registers are intended to be used for te sting and diagnostic purposes, except the control/status regis- ters and watermark for initialization. manipulating the contents of these registers under ?normal? running conditions is not recommended and may lead to undefined results. if the default values are acceptable, the watermark should not be written (for futu re backward compatibility, if wa- termarks/fifo depth are adapted). the watermark of the transmit queues must not be set to zero. for each transmit queue in each link a separate set of registers is implemented. the following register set is implemented for asynchronous transmit queue. fifo write shadow level (offset: 0x4f, width: 8) 7:0 fifo write shadow level (qword) ne value 0 bit name description write read reset (sw) transmit queue registers current transmit descriptor (offset: 0x00, width: 2 x 16) 31:16 transmit buffer control to value 0 15:0 transmit buffer byte count to value 0 transmit buffer address (offset: 0x08, width: 2 x 32) 31:0 transmit buffer address lo lower part of transmit buffer address to value 0 31:0 transmit buffer address hi higher part of transmit buffer address to value 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 166 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications transmit buffer status word (offset: 0x10, width: 32) 31:0 tfsw transmit frame status word as defined by the mac. appended to transmit data of this buffer, if eof is set. this is a placeholder, because gmac does not expect a transmit frame status word. default value is 0. in loopback mode transmit frame status word has to be set to the expected re- ceive frame status word of gmac. defined by the host, if eof is set to value 0 tcp/ip checksum extension (offset: 0x18, width: 4 x 16) 31:16 reserved 15:0 tcp sum init checksum, start value defined by the host, if stf is set. the byte order within the tcp sum init value is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). during tcp sum calculation the msb is added to the first, third and so on byte of the packet. the lsb is added to the sec- ond, forth and so on byte of the packet. to value 0 31:16 tcp sum start checksum, start position for calculation in bytes (16-bit-aligned) counted from zero (first byte = 0) defined by the host, if stf is set. to value 0 15:0 tcp sum write checksum, write position for checksum in bytes (16-bit-aligned) counted from zero (first byte = 0) defined by the host, if stf is set. to value 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 167 register description control register file vlan tag (offset: 0x20, width: 16) 31:16 reserved 15:0 vlan tag transmit vlan tag bytes extracted from received descriptor of host buffer the byte order within the vlan tag val- ue is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). to value 0 done index (offset: 0x24, width: 16) 31:12 reserved 11:0 done index incremented for each processed list ele- ment to value 0 request address (offset: 0x28, width: 2 x 32) 31:0 request addr lo lower 32 bit of current request address to value 0 31:0 request addr hi higher 32 bit of current request address to value 0 request byte count (offset: 0x30, width: 16) 31:11 reserved 10:0 request byte count length of current request in number of bytes to value 0 bmu control/status register (offset: 0x34, width: 32) 31 bmu idle status bit bmu in idle state ne value 1 30:14 reserved 13 ip id increment enable enables/disables incrementing of the ip identification field with every segment during tcp segmentation. default: disabled (0b01) exec 0b10 0 12 ip id increment disable 0b01 1 11 clear irq tcp clear irq on tcp segmentation length mismatch exec 0 0 10 clear irq check clear irq check. (this interrupt is asserted when receiving a wrong opcode within a list element) exec 0 0 9 stop tx bmu 10: stop transmit queue transfer after next end of packet 01: normal operation (default) exec 0b10 0 8 start tx bmu 0b01 1 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 168 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 7 fifo operational on default: off (0b01) must be switched to on after initialization exec 0b10 0 6 fifo operational off 0b01 1 5 fifo enable default: reset (0b01) exec 0b10 0 4 fifo reset 0b01 1 3 bmu operational on default: off (0b01) must be switched to on after initialization exec 0b10 0 2 bmu operational off 0b01 1 1 bmu enable default: reset (0b01) exec 0b10 0 0 bmu reset 0b01 1 bmu test register (offset: 0x38, width: 32) 31:23 reserved 22 testmode shad- ow read ptr on switch to testmode shadow read point- er default: operation (testmode = off) exec 0b10 0 21 testmode shad- ow read ptr off 0b01 1 20 teststep shadow read ptr teststep: increment shadow read point- er exec 0 0 19 reserved 18 testmode read ptr on switch to testmode read pointer default: operation (testmode = off) exec 0b10 0 17 testmode read ptr off 0b01 1 16 teststep read ptr teststep: increment read pointer exec 0 0 15 reserved 14 testmode shad- ow write ptr on switch to testmode shadow write point- er default: operation (testmode = off) exec 0b10 0 13 testmode shad- ow write ptr off 0b01 1 12 teststep shadow write ptr teststep: increment shadow write point- er exec 0 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 169 register description control register file 11 reserved 10 testmode write ptr on switch to testmode write pointer default: operation (testmode = off) exec 0b10 0 9 testmode write ptr off 0b01 1 8 teststep write ptr teststep: increment write pointer exec 0 0 7 reserved 6 testmode req nbytes/addr on switch to testmode request nbytes/ad- dresses default: operation (testmode = off) exec 0b10 0 5 testmode req nbytes/addr off 0b01 1 4 teststep req nbytes/addr teststep request nbytes/addresses an acknowledge from biu is emulated and as a result address counter is incre- mented by nbytes and nbytes is reset to zero. exec 0 0 3 reserved 2 testmode done index on switch to testmode done index default: operation (testmode = off) exec 0b10 0 1 testmode done index off 0b01 1 0 teststep done in- dex teststep: increment done index exec 0 0 bmu statemachine register (offset: 0x3c, width: 32) 31:0 state variables of all statemachines to value 0x00 (idle state) fifo watermark (offset: 0x40, width: 11) 15:11 reserved 10:0 fifo watermark (bytes) yes aw 0x600 fifo alignment (offset: 0x42, width: 8) 15:7 reserved 6:4 mux multiplexer setting ne value 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 170 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3 reserved 2:0 vram vram position ne value 0 fifo write shadow pointer (offset: 0x44, width: 16) 15:11 reserved 10:0 fifo write shadow pointer (bytes) to value 0 fifo write shadow level (offset: 0x46, width: 8) 15:8 reserved 7:0 fifo write level (qword) ne value 0 fifo write pointer (offset: 0x48, width: 8) 15:8 reserved 7:0 fifo write pointer (qword) to value 0 fifo write level (offset: 0x4a, width: 8) 15:8 reserved 7:0 fifo write level (qword) ne value 0 fifo read pointer (offset: 0x4c, width: 8) 15:8 reserved 7:0 fifo read pointer (qword) to value 0 fifo read level (offset: 0x4e, width: 8) 15:8 reserved 7:0 fifo read level (qword) ne value 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 171 register description control register file 3.3.2.43 prefetch unit registers address: base address width [bit]:6 x 32 address: base address + 0x20 width [bit]:4 x 8 each transmit or receive queue has its dedicated prefetch fifo and the pr efetch unit registers. base addresses for the pref etch unit register sets: the register address of each register is calcul ated by adding the base address and the offset. due to a smaller pfu fifo for transmit queues, the size of the pointers and levels is to be decreased by one for transmit pfus. queue base address rx 0x0450 tx 0x06d0 bit name description write read reset (link) prefetch control register (offset: 0x00, width: 32) 31:15 reserved 14 master request loopback test on testmode on/off for the master re- quest, i.e. enables the stepping of the master request by the sw. the default operation is disabled. exec 0b10 0 13 master request loopback test off 0b01 1 12 master request loopback step enables the loopback of a single master request. for execution of this command, the mas- ter request loopback test must be set to on. exec 0 0 11 reserved 10 fifo read pointer test on testmode on/off for the fifo read pointer, i.e. enables the stepping of the pointer by the sw. the default operation is disabled. exec 0b10 0 9 fifo read pointer test off 0b01 1 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 172 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 8 fifo read pointer step fifo read pointer increment. for execution of this command, the fifo read pointer test must be set to on. exec 0 0 7 reserved 6 fifo write pointer test on testmode on/off for the fifo write pointer, i.e. enables the stepping of the pointer by the sw. the default operation is disabled. exec 0b10 0 5 fifo write pointer test off 0b01 1 4 fifo write pointer step fifo write pointer increment. for execution of this command, the fifo write pointer test must be set to on. exec 0 0 3 operational on operational mode on/off off resets all activities of the prefetch unit for initialization of the pointers and registers. the default operation is disabled. exec 0b10 0 2 operational off 0b01 1 1 pfu reset clear set/clear pfu reset. executed, if appropriate bit is set to 1. if pfu reset is set, the integrated pfu and the pfu target interface are in their reset state. exec 0b10 0 0 pfu reset set 0b01 1 list last index (offset: 0x04, width: 12) 31:12 reserved 11:0 list last index specifies the index of the last entry in the list. the descriptor element length is de- fined by list last index + 1. the length is given as number of list ele- ments bit 6:0: fixed value 0x7f yes aw 0x07f list start address low (offset: 0x08, width: 32) 31:12 identifies the lower 32 bit of the start ad- dress of the descripto r list in the system memory. yes aw 0x0 11:0 the address is always aligned to 4 kb boundaries, i.e. the lower bits are always 0x0. ne 0x0 0x0 bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 173 register description control register file list start address high (offset: 0x0c, width: 32) 31:0 identifies the upper 32 bit of the start ad- dress of the descriptor list in the system memory. yes aw 0x0 get index (offset: 0x10, width: 32) 31:12 reserved 11:0 specifies the pop/ rd address within the descriptor list in system memory. this get index points to the address of the next element to be fetched. if get index and put index are equal, no element is in the fifo the index is given in list element granu- larity. yes value 0x0 put index (offset: 0x14, width: 12) 31:12 reserved 11:0 specifies the push/wr address within the descriptor list in system memory. this put index points to the address of the next free element in the descriptor list (i.e. the position after the last valid ele- ment in the descriptor list). if get index and put index are equal, no element is in the fifo. the index is given in list element granu- larity. yes aw 0x0 fifo ram write and write shadow pointer (offset: 0x20, width: 32) 31:24 reserved 23:16 fifo wr ptr specifies the push/wr pointer to the in- ternal prefetch fifo ram. the pointer is given in bytes. yes value 0x0 fifo ram write pointer 15:5 reserved 4:0 fifo rd ptr specifies the push/wr pointer to the in- ternal prefetch fifo ram. the pointer is given in list element granu- larity (qwords). yes value 0x0 bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 174 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications fifo ram read pointer (offset: 0x24, width: 6) 31:5 reserved 4:0 fifo rd ptr specifies the pop/rd pointer to the inter- nal prefetch fifo ram. the pointer is given in list element granu- larity. yes value 0x0 master request nbytes (offset: 0x28, width: 32) 31:27 reserved 26:16 master request nbytes specifies the number of bytes requested from the master. this value is used only for debugging purpose. the number is given in bytes no value 0x0 fifo watermark 15:6 reserved 5:0 fifo watermark specifies the watermark level (i.e. free el- ements level) for prefetching new de- scriptor elements. the watermark is given in list element granularity. yes aw 0x0 bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 175 register description control register file 3.3.2.44 receive ra mbuffer registers address: 0x0800 - 0x0828 width [bit]: 11 x 32 (receive queue, structure as shown below) initialization or re-arrangement of a ramb uffer should ever start from reset state. fifo shadow level (offset: 0x2c, width: 32) 31:24 reserved 23:16 fifo shadow level specifies the current filling level of the prefetch fifo ram. th is value is directly updated by the read and write accesses to the fifo ram. this value is used for debugging purpose only. the number is given in bytes. yes value ram size fifo level 15:5 reserved 4:0 fifo level specifies the current filling level of the prefetch fifo ram. th is value is directly updated by the read and write accesses to the fifo ram. this value is used for debugging purpose only. the number is given in list element gran- ularity (qwords). yes value ram size bit name description write read reset (pri- vate) receive rambuffer start address (offset: 0x00, width: 32) 31:13 reserved 12:0 start address start address in qwords of this queue in internal memory. bit [7:0] are replaced by zeroes inter- nally, which means that the address is limited to multiples of 1 kb. has to be defined after each reset. yes (for init/ tests only) aw 0 bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 176 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications receive rambuffer end address (offset: 0x04, width: 32) 31:13 reserved 12:0 end address end address in qwords of this queue in internal memory. bit [7:0] are replaced by ones internally, which means that th e address is limited to multiples of 1 kb. has to be defined after each reset. yes (for init/ tests only) aw 0 receive buffer write pointer (offset: 0x08, width: 32) 31:13 reserved 12:0 write pointer write pointer in qwords. has to be set to receive rambuffer start address after each reset. yes (for init/ tests only) value 0 receive rambuffer read pointer (offset: 0x0c, width: 32) 31:13 reserved 12:0 read pointer read pointer in qwords has to be set to receive rambuffer start address after each reset. yes (for init/ tests only) value 0 receive rambuffer upper threshold/pause packets (offset: 0x10, width: 32) 31:13 reserved 12:0 upper threshold/ pause packets if this queue is filled up to this threshold, signal xmtpausepkt of the mac is as- serted (if en pause is set). multiples of 8 bytes. no effect, if set to zero. yes (for init/ tests only) aw 0 bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 177 register description control register file receive rambuffer lower threshold/pause packets (off- set: 0x14, width: 32) 31:13 reserved 12:0 lower threshold/ pause packets signal xmtpausepkt of the mac is deas- serted, if the number of bytes falls below lower threshold. multiples of 8 bytes. yes (for init/ tests only) aw 0 receive rambuffer upper threshold/high priority (offset: 0x18, width: 32) 31:13 reserved 12:0 upper threshold/ high priority if this queue is filled up to this threshold, all arbiters grant highest priority to the re- quests of this queue. multiples of 8 bytes. no effect, if set to zero. to aw 0 receive rambuffer lower threshold/high priority (offset: 0x1c, width: 32) 31:13 reserved 12:0 lower threshold/ high priority all arbiters grant normal priority to the re- quests of this queue, if the number of bytes falls below lower threshold. multiples of 8 bytes. yes (for init/ tests only) aw 0 receive rambuffer packet counter (offset: 0x20, width: 32) 31:13 reserved 12:0 packet counter packet counter gives the current number of packets in this queue. yes (for tests only) value 0 receive rambuffer level (offset: 0x24, width: 32) 31:13 reserved 12:0 level level gives the current number of data in multiples of 8 bytes in this queue (includ- ing 16 bytes statusword per packet). ne value 0 bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 178 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications receive rambuffer control/test (offset: 0x28, width: 32) te s t 31:20 reserved 19 packet counter step down packet counter decrement exec 0 18 packet counter test on testmode on/off exec 0b10 0 17 packet counter test off 0b01 1 16 packet counter step up packet counter increment exec 0 15 reserved 14 write pointer test on testmode on/off for testmode on this rambuffer queue must be set to non operational exec 0b10 0 13 write pointer test off 0b01 1 12 write pointer step write pointer increment exec 0 11 reserved 10 read pointer test on testmode on/off for testmode on this rambuffer queue must be set to non operational exec 0b10 0 9 read pointer test off 0b01 1 8 read pointer step read pointer decrement exec 0 control/status 7:6 reserved 5 st&fwd on store and forward on/off if on, a frame is forwarded from ram- buffer only, if the complete frame is in rambuffer. exec 0b10 0 4 st&fwd off 0b01 1 bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 179 register description control register file 3 operational on operational mode on/off off resets all activiti es of this rambuffer queue for initialization of the pointers and registers exec 0b10 0 2 operational off 0b01 1 1 reset clear set/clear reset. executed, if appropriate bit is set to 1. if reset is set, all receive rambuffer functions and registers are in their reset state. exec 0b10 0 (sw) 0 reset set 0b01 1 (sw) bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 180 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.45 transmit rambuffer registers address: 0x0a80 - 0x0aa8 width [bit]: 7 x 32 (asynchronous transmit queue) initialization or re-arrangement of a rambuf fer should ever start from reset state. bit name description write read reset (pri- vate) transmit rambuffer start address (offset: 0x00, width: 32) 31:13 reserved 12:0 start address start address in qwords of this queue in internal memory. bit [7:0] are replaced by zeroes inter- nally, which means that the address is limited to multiples of 1 kb. has to be defined after each reset. yes (for init/ tests only) aw 0 transmit rambuffer end address (offset: 0x04, width: 32) 31:13 reserved 12:0 end address end address in qwords of this queue in internal memory. bit [7:0] are replaced by ones internally, which means that th e address is limited to multiples of 1 kb. has to be defined after each reset. yes (for init/ tests only) aw 0 transmit rambuffer write pointer (offset: 0x08, width: 32) 31:13 reserved 12:0 write pointer write pointer in qwords. has to be set to transmit rambuffer start address after each reset. yes (for init/ tests only) value 0 transmit rambuffer read pointer (offset: 0x0c, width: 32) 31:13 reserved 12:0 read pointer read pointer in qwords. has to be set to transmit rambuffer start address after each reset. yes (for init/ tests only) value 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 181 register description control register file packet counter (offset: 0x20, width: 32) 31:13 reserved 12:0 packet counter packet counter provides the current number of packets in this queue. yes (for tests only) value 0 transmit rambuffer level (offset: 0x24, width: 32) 31:13 reserved 12:0 level level gives the current number of data in multiples of 8 bytes in this queue (includ- ing 16 bytes statusword per packet). ne value 0 rambuffer control/test (offset: 0x28, width: 32) te s t 31:20 reserved 19 packet counter step down packet counter decrement exec 0 18 packet counter test on testmode on/off exec 0b10 0 17 packet counter test off 0b01 1 16 packet counter step up packet counter increment exec 0 15 reserved 14 write pointer test on testmode on/off for testmode on this rambuffer queue must be set to non operational exec 0b10 0 13 write pointer test off 0b01 1 12 write pointer step write pointer increment exec 0 11 reserved bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 182 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 10 read pointer test on testmode on/off for testmode on this rambuffer queue must be set to non operational exec 0b10 0 9 read pointer test off 0b01 1 8 read pointer step read pointer decrement exec 0 control/status 7 reserved 6 reserved 5 st&fwd on store and forward on/off if on, a frame is forwarded from ram- buffer only, if the complete frame is in rambuffer. if on, this overrides the control on a per frame base as defined by the transmit descriptor. because most pci systems do not pro- vide gigabit ethernet bandwidth, st&fwd should be switched on for the transmit rambuffer(s). exec 0b10 0 4 st&fwd off 0b01 1 3 operational on operational mode on/off off resets all activities of this rambuffer queue for initialization of the pointers and registers exec 0b10 0 2 operational off 0b01 1 1 reset clear set/clear reset. executed, if appropriate bit is set to 1. if reset is set, all transmit rambuffer functions and registers are in their reset state. exec 0b10 0 (sw) 0 reset set 0b01 1 (sw) bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 183 register description control register file 3.3.2.46 receive m ac fifos registers address: 0x0c40 width [bit]: 7 x 32 initialization or re-arrangement of a mac fifo should ever start from reset state. bit name description write read reset (pri- vate) receive mac fifo end address (offset: 0x00, width: 32) 31:7 reserved 6:0 end address end address in qwords of this queue in internal dual port memory. max = reset value, min = 0x04 reset value should be used. yes (for init/ tests only) aw 0x7f receive mac fifo almost full threshold (offset: 0x04, width: 32) 31:7 reserved 6:0 almost full threshold almost full threshold in qwords yes (for tests only) value 0x70 receive mac fifo control/test (offset: 0x08, width: 32) 31:28 reserved 27 truncation enable controls truncation of packets within fifo default: disabled 0b01 exec 0b10 0 26 truncation dis- able 0b01 1 25 vlan enable enables/disables vlan stripping default: disabled 0b01 exec 0b10 0 24 vlan disable 0b01 1 23:15 reserved 14 write pointer test on testmode on/off exec 0b10 0 13 write pointer test off 0b01 1 12 write pointer step write pointer increment exec 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 184 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 11 reserved 10 read pointer test on testmode on/off exec 0b10 0 9 read pointer test off 0b01 1 8 read pointer step read pointer increment exec 0 receive mac fifo control 7 fifo flush on fifo flush mode on/off when set to on packets of size below the fifo flush threshold are flushed, if a bit of its status matches a one in the fifo flush mask. when set to off no packets are flushed. exec 0b10 0 6 fifo flush off 0b01 1 5 clear irq receive fifo overrun receive fifo overrun interrupt exec 0 4 clear irq frame reception com- plete frame reception complete interrupt exec 0 3 operational on operational mode on/off off resets all activities of this fifo for initialization of the pointers and registers exec 0b10 0 2 operational off 0b01 1 1 mac fifo reset clear set/clear mac fifo reset. executed, if appropriate bit is set to 1. if mac fifo reset is set, all fifo func- tions and registers are in their reset state. exec 0b10 0 (sw) 0 mac fifo reset set 0b01 1 (sw) receive mac fifo flush mask (offset: 0x0c, width: 32) 31:15 reserved 14 length error 13 vlan packet yes aw 0 12 jabber yes aw 0 bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 185 register description control register file 11 undersize packet yes aw 0 10 multicast packet yes aw 0 9 broadcast packet yes aw 0 8 receive ok yes aw 0 7 good flow con- trol packet yes aw 0 5 mii error yes aw 0 4 too long packet yes aw 0 3 fragment yes aw 0 2 reserved yes aw 0 1 crc error yes aw 0 0 receive fifo overflow yes aw 0 receive mac fifo flush threshold (offset: 0x10, width: 32) 31:7 reserved 6:0 flush threshold the flush threshold is defined in fifo words (8 bytes). yes aw 0x0a receive truncation threshold (offset: 0x14, width: 32) 31:7 reserved 6:0 truncation threshold the truncation threshold is defined in fifo words (8 bytes). loaded with the desired number of re- ceive dwords -2. example: for the acceptance of only the first ten bytes of a packet a value of eight is written into this register. yes aw 0x0a receive vlan type register (offset: 0x1c, width: 32) 31:16 reserved bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 186 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 15:0 receive vlan type code of received vlan type. default: 0x8100 the byte order within the vlan type val- ue is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). yes (for tests only) value 0x8100 receive mac fifo write pointer (offset: 0x20, width: 32) 31:7 reserved 6:0 write pointer write pointer in qwords of this queue in internal dual port memory. yes (for tests only) value 0 receive mac fifo write level (offset: 0x28, width: 32) 31:7 reserved 6:0 write level level gives the current number of data in multiples of 8 bytes in this queue (includ- ing 16 bytes statusword per packet). ne value 0 receive mac fifo read pointer (offset: 0x30, width: 32) 31:7 reserved 6:0 read pointer read pointer in qwords of this queue in internal dual port memory. yes (for tests only) value 0 receive mac fifo read level (offset: 0x38, width: 32) 31:7 reserved 6:0 read level level gives the current number of data in multiples of 8 bytes in this queue (includ- ing 16 bytes statusword per packet). ne value 0 bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 187 register description control register file 3.3.2.47 transmit mac fifos registers address: 0x0d40 width [bit]: 10 x 32 bit name description write read reset (pri- vate) transmit mac fifo end address (offset: 0x00, width: 32) 31:7 reserved 6:0 end address end address in qwords of this queue in internal dual port memory. max = reset value, min = 0x04 reset value should be used. yes (for init/ tests only) aw 0x7f transmit mac fifo almost empty threshold (offset: 0x04, width: 32) 31:7 reserved 6:0 almost empty threshold almost empty threshold in qwords yes (for tests only) value 0x10 transmit mac fifo control/test (offset: 0x08, width: 32) 31:26 reserved 25 vlan enable enables/disables vlan tagging default: disabled 0b01 exec 0b10 0 24 vlan disable 0b01 1 23:19 reserved 18 write shadow pointer test on testmode on/off exec 0b10 0 17 write shadow pointer test off 0b01 1 16 write shadow pointer step write pointer increment exec 0 15 reserved marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 188 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 14 write pointer test on testmode on/off exec 0b10 0 13 write pointer test off 0b01 1 12 write pointer step write pointer increment exec 0 11 reserved 10 read pointer test on testmode on/off exec 0b10 0 9 read pointer test off 0b01 1 8 read pointer step read pointer increment exec 0 transmit mac fifo control 7 reserved 6 clear irq trans- mit fifo under- run transmit fifo underrun interrupt exec 0 5 clear irq frame transmission complete frame transmission complete interrupt exec 0 4 clear irq parity error clear parity error interrupt exec 0 3 operational on operational mode on/off off resets all activities of this fifo for initialization of the pointers and registers exec 0b10 0 2 operational off 0b01 1 1 mac fifo reset clear set/clear mac fifo reset. executed, if appropriate bit is set to 1. if mac fifo reset is set, all fifo func- tions and registers are in their reset state. exec 0b10 0 (sw) 0 mac fifo reset set 0b01 1 (sw) transmit vlan type register (offset: 0x1c, width: 32) 31:16 reserved bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 189 register description control register file 15:0 transmit vlan type code of transmitted vlan type. default: 0x8100 the byte order within the vlan type val- ue is big endian: the msb is in the lower byte (bit 7:0) and the lsb is in the higher byte (bit 15:8). yes (for tests only) value 0x8100 transmit mac fifo write pointer (offset: 0x20, width: 32) 31:7 reserved 6:0 write pointer write pointer in qwords of this queue in internal dual port memory. yes (for tests only) value 0 transmit mac fifo write shadow pointer (offset: 0x24, width: 32) 31:7 reserved 6:0 write shadow pointer write shadow pointer in qwords of this queue in internal dual port memory. yes (for tests only) value 0 transmit mac fifo write level (offset: 0x28, width: 32) 31:7 reserved 6:0 write level level gives the current number of data in multiples of 8 bytes in this queue (includ- ing 16 bytes statusword per packet). ne value 0 transmit mac fifo read pointer (offset: 0x30, width: 32) 31:7 reserved 6:0 read pointer read pointer in qwords of this queue in internal dual port memory. yes (for tests only) value 0 transmit mac fifo restart pointer (offset: 0x34, width: 32) 31:7 reserved bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 190 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.48 descriptor poll timer registers address: 0x0e00 width [bit]: 3 x 32 the poll timer generates a periodical trigger signal for all bmus setting start xxx such initiating a descriptor read. this may be enabled for each bmu individually through en polling in the bmu?s control/status registers . 6:0 restart pointer restart pointer in qwords of this queue in internal dual port memory. yes (for tests only) value 0 transmit mac fifo read level (offset: 0x38, width: 32) 31:7 reserved 6:0 read level level gives the current number of data in multiples of 8 bytes in this queue (includ- ing 16 bytes statusword per packet). ne value 0 bit name description write read reset (sw) descriptor poll timer init value 31:0 init value descriptor poll timer init value yes aw 0 descriptor poll timer 31:0 descriptor poll timer multiples of core clock (125 mhz) cycle time t max = 27.53 s to value 0 descriptor poll timer control/test te s t 31:19 reserved 18 descriptor poll timer test on testmode on/off exec 0b10 0 17 descriptor poll timer test off 0b01 1 bit name description write read reset (pri- vate) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 191 register description control register file the timer implements write posting and retries the follo wing accesses to the timer while a posted write is in progress. target reads are retried until the addresse d register is synchronized to pci clock. 3.3.2.49 timestamp timer registers address: 0x0e10 width [bit]: 3 x 32 the timestamp timer generates the timebase for the timestamp, which is passed to each frame?s descriptor. when wrapping around from 0x ffff_ffff to 0x0000_ 0000 it generates an interrupt. 16 descriptor poll timer step timer decrement exec 0 15:8 reserved control 7:3 reserved 2 descriptor poll timer start start/stop timer exec 0b10 0 1 descriptor poll timer stop 0b01 1 0 reserved bit name description write read reset (sw) 31:0 reserved timestamp timer 31:0 timestamp timer multiples of core clock (125 mhz) cycle time yes (for tests only) value 0 timestamp timer control/test te s t 31:11 reserved bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 192 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications the timer implements write posting and retries the follo wing accesses to the timer while a posted write is in progress. target reads are retried until the addressed register is synchronized to pci clock. 3.3.2.50 polling unit registers address: 0x0e20 width [bit]: 4 x 32 10 timestamp timer test on testmode on/off exec 0b10 0 9 timestamp timer test off 0b01 1 8 timestamp timer step timer increment exec 0 control 7:3 reserved 2 timestamp timer start start/stop timer when started, timer starts counting from value zero. exec 0b10 0 1 timestamp timer stop 0b01 1 0 timestamp timer clear irq clear timer interrupt exec 0 bit name description write read reset (link) poll control register (address: 0x0e20, width: 32) 31:6 reserved 5 clear irq clears the check irq generated by the polling unit. exec 0 0 4 poll request for testing purpose a poll request can be started by sw by writing a 1 to this bit. exec 0 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 193 register description control register file 3 operational on operational mode on/off off resets all activities of the polling unit for initialization of the pointers and regis- ters. the default operation is disabled. exec 0b10 0 2 operational off 0b01 1 1 pollu reset clear set/clear poll unit reset. executed, if appropriate bit is set to 1. if poll unit reset is set, the integrated pollu and the pollu target interface are in their reset state. exec 0b10 0 0 pollu reset set 0b01 1 list last index (address: 0x0e24, width: 12)) 31:12 reserved 11:0 list last index specifies the index of the last entry in the list. the descriptor element length is de- fined by list last index + 1. the length is given as number of list ele- ments. the length is fixed. only 2 le (dual link version) are read each time. no 0x001 0x001 list start address low (address: 0x0e28, width: 32) 31:3 identifies the lower 32 bit of the start ad- dress of the descriptor list in the system memory. yes aw 0x0 2:0 the address is always aligned to de- scriptor list element size, i.e. 8 byte boundaries, i.e. the lower bits are always 0x0. ne 0x0 0x0 list start address high (address: 0x0e2c, width: 32) 31:0 identifies the upper 32 bit of the start ad- dress of the descriptor list in the system memory. yes aw 0x0 bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 194 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.51 status unit registers address: 0x0e80 width [bit]: 24 x 32 bit name description write read reset (sw) status unit registers status bmu control (offset: 0x00, width: 32) 31:19 reserved 18 master request loopback test on testmode on/off for the master re- quest, i.e. enables the stepping of the master request by the sw. the default operation is disabled. exec 0b10 0 17 master request loopback test off 0b01 1 16 master request loopback step enables the loopback of a single master request. for execution of this command, the mas- ter request loopback test must be set to on. exec 0 0 15 reserved 14 fifo read pointer test on testmode on/off for the fifo read pointer, i.e. enables the stepping of the pointer by the sw. the default operation is disabled. exec 0b10 0 13 fifo read pointer test off 0b01 1 12 fifo read pointer step fifo read pointer increment. for execution of this command, the fifo read pointer test must be set to on. exec 0 0 11 reserved 10 fifo write pointer test on testmode on/off for the fifo write pointer, i.e. enables the stepping of the pointer by the sw. the default operation is disabled. exec 0b10 0 9 fifo write pointer test off 0b01 1 8 fifo write pointer step fifo write pointer increment. for execution of this command, the fifo write pointer test must be set to on. exec 0 0 7:5 reserved marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 195 register description control register file 4 clear irq status bmu clear status bmu interrupt exec 0 3 operational on default off exec 0b10 0 2 operational off 0b01 1 1 enable default reset exec 0b10 0 0 reset 0b01 1 last index (offset: 0x04, width: 16) 31:12 reserved 11:0 last index index of last element of current list bit 6:0: fixed value 0x7f list length is a multiple of 128 elements. yes aw 0x007f list start address (offset: 0x08, width: 2 x 32) 31:0 list start ad- dress lo lower part of list start address bit 11:0: fixed value 0x000 address aligned to 4 kbyte boundaries. yes aw 0 31:0 list start ad- dress hi higher part of list start address yes aw 0 txa report index (offset: 0x10, width: 16) 15:12 reserved 11:0 txa report index last reported tx done index for txa queue ne value 0 15:0 reserved tx index threshold (offset: 0x18, width: 16) 15:12 reserved 11:0 tx index thresh- old a status burst is initiated when exceeding the threshold. yes aw 0xfff bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 196 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications put index (offset: 0x1c, width: 16) 31:12 reserved 11:0 specifies the push/wr address within the descriptor list in system memory. this put index points to the address of the next free element in the descriptor list (i.e. the position afte r the last valid ele- ment in the descriptor list). if get index and put index are equal, no element is in the fifo. the index is given in list element granu- larity. yes aw 0x0 fifo write pointer (offset: 0x20, width: 8) 31:6 reserved 5:0 fifo write pointer (64 qword fifo) to value 0 fifo read pointer (offset: 0x24, width: 8) 31:6 reserved 5:0 fifo read pointer (qword) to value 0 fifo level (offset: 0x28, width: 8) 31:6 reserved 5:0 fifo level (qword) ne value 0 fifo watermark (offset: 0x2c, width: 8) 7:6 reserved 5:0 fifo watermark (qword) yes aw 0x30 fifo isr watermark (offset: 0x2d, width: 8) 7:6 reserved 5:0 fifo isr watermark (qword) watermark relevant during interrupt ser- vice routine. yes aw 0x08 level timer level timer init value (offset: 0x30, width: 32) 31:0 level timer init value level timer init value yes aw 0x3d09 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 197 register description control register file level timer counter (offset: 0x34, width: 32) 31:0 level timer multiples of core clock (125 mhz) cycle time t max = 27.53 s to value 0 level timer control/test (offset: 0x38, width: 32) te s t 31:11 reserved 10 level timer test on testmode on/off exec 0b10 0 9 level timer test off 0b01 1 8 level timer step timer decrement exec 0 control 7:3 reserved 2 level timer start start/stop level timer exec 0b10 0 1 level timer stop 0b01 1 0 reserved tx timer tx timer init value (offset: 0x40, width: 32) 31:0 tx timer init value tx timer init value yes aw 0 tx timer counter (offset: 0x44, width: 32) 31:0 tx timer multiples of core clock (125 mhz) cycle time t max = 27.53 s to value 0 tx timer control/test (offset: 0x48, width: 32) te s t 31:11 reserved 10 tx timer test on testmode on/off exec 0b10 0 9 tx timer test off 0b01 1 8 tx timer step timer decrement exec 0 bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 198 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications control 7:3 reserved 2 tx timer start start/stop tx timer exec 0b10 0 1 tx timer stop 0b01 1 0 reserved isr timer isr timer init value (offset: 0x50, width: 32) 31:0 isr timer init value isr timer init value yes aw 0 isr timer counter (offset: 0x54, width: 32) 31:0 isr timer multiples of core clock (125 mhz) cycle time t max = 27.53 s to value 0 isr timer control/test (offset: 0x58, width: 32) te s t 31:11 reserved 10 isr timer test on testmode on/off exec 0b10 0 9 isr timer test off 0b01 1 8 isr timer step timer decrement exec 0 control 7:3 reserved 2 isr timer start start/stop isr timer exec 0b10 0 1 isr timer stop 0b01 1 0 reserved bit name description write read reset (sw) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 199 register description control register file 3.3.2.52 mac control registers address: 0x0f00 width [bit]:8 bit name description write read reset (link) mac control register 15:8 reserved 7 en burstmode on enables the fifo to signal gmac, that enough packets are available to enter half duplex burst mode. exec 0b10 0 6 en burstmode off 0b01 1 5 loopback on the gmac interface may be set to loop- back mode for testing purposes. transmit data is looped to receive data. there is no activity at the related gmac control signals. the transmit status (descriptors) must be set to the expected receive status (descriptors). exec 0b10 0 4 loopback off 0b01 1 3 en pause on enable forwarding of the signal xmt- pausepkt to gmac see also receive rambuffer upper/ lower threshold/pause packets must be switched off in loopback mode. settings for gmac must be consistent. exec 0b10 0 2 en pause off 0b01 1 1 gmac reset clear set/clear gmac reset. executed, if appropriate bit is set to 1. if gmac reset is set, the integrated gmac and the gmac target interface are in their reset state. in order to guarantee a minimum pulse width of 31 core clock cycles, clearing gmac reset is suppressed within 31 core clock cycles after gmac reset set . write cycles to gmac reset clear with- in the 31 core clock recovery time, are terminated with a target retry (no impact on software). exec 0b10 0 0 gmac reset set 0b01 1 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 200 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.53 phy mux register and phy control register address: 0x0f04 width [bit]:8 + 24 the phy control register contains settings for the phy. the meaning of the seven configuration pins is descri bed in "88e1111 integrated 10/100/1000 gigabit ethernet transceiver", marvell, doc. no. mv-s100707-00 - hardware configuration. bit name description write read reset (link) phy mux register, loaded from external memory 31:29 reserved 28:26 mux6 3 bit multiplexer setting for config6 pin yes aw 0b000 25:23 mux5 3 bit multiplexer setting for config5 pin yes aw 0b000 22:20 mux4 3 bit multiplexer setting for config4 pin yes aw 0b000 19:17 mux3 3 bit multiplexer setting for config3 pin yes aw 0b000 16:14 mux2 3 bit multiplexer setting for config2 pin yes aw 0b000 13:11 mux1 3 bit multiplexer setting for config1 pin yes aw 0b000 10:8 mux0 3 bit multiplexer setting for config0 pin yes aw 0b000 phy control register 7:2 reserved 1 phy reset clear set/clear phy reset. executed, if appropriate bit is set to 1. if phy reset is set, the integrated phy is in its reset state. in order to guarantee a minimum pulse width of 31 core clock cycles, clearing phy reset is suppressed within 31 core clock cycles after phy reset set . write cycles to phy reset clear within the 31 core clock recovery time, are terminated with a target retry (no impact on soft- ware). exec 0b10 0 0 phy reset set 0b01 1 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 201 register description control register file 3.3.2.54 mac interrupt source register address:0x0f08 width [bit]:8 if set to one, interrupt is pending. table 28: pin to constant mapping (mux to config pins) pin bit<2:0> vdd (=1) 111 led_link10/100 101 led_link1000 100 led_linkn 011 led_actn 010 vss (=0) 000 bit name description write read reset (sw) mac interrupt source register 31:6 reserved 5 transmit counter overflow inter- rupt one or more bits are set in the transmit counter interrupt register ne value 0 4 receive counter overflow inter- rupt one or more bits are set in the receive counter interrupt register . ne value 0 3 transmit fifo underrun underrun condition in the tx mac fifo ne value 0 2 frame transmis- sion complete frame transmission complete. frame is copied from the tx mac fifo and transmitted by the mac successful- ly ne value 0 1 receive fifo overrun overflow condition in the rx mac fifo ne value 0 0 frame reception complete frame reception complete. frame is copied into the rx mac fifo successfully ne value 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 202 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.55 mac interrupt mask register address: 0x0f0c width [bit]:8 the enable bits have the same bit positions as in the mac interrupt source register. if set to one, interrupt is enabled. 3.3.2.56 link control register address: 0x0f10 width [bit]:8 the link control register contains settings for the parts needed to establish a link. bit name description write read reset (sw) mac interrupt mask register 31:0 en irq xxx enable interrupt xxx yes aw 0 bit name description write read reset (power on) link control register 15:2 reserved 1 link reset clear set/clear link reset. executed, if appropriate bit is set to 1. if link reset is set, the wol unit , the mac control register and the phy control register are in their reset state. this also implies that the integrated gmac and phy are also in their reset state. exec 0b10 0 0 link reset set 0b01 1 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 203 register description control register file 3.3.2.57 wake on lan control registers base address: 0x0f20 width [bit]:8 x 32 the wake on lan control registers are used to contro l the wake up frame unit, the magic pattern unit and the link change unit. bit name description write read reset (link) match result register (offset: 0x03, width: 8) 31 reserved 30 pattern 6 match if set, the last incoming packet matched with pattern number ne value 0b0 29 pattern 5 match ne value 0b0 28 pattern 4 match ne value 0b0 27 pattern 3 match ne value 0b0 26 pattern 2 match ne value 0b0 25 pattern 1 match ne value 0b0 24 pattern 0 match ne value 0b0 match control register (offset: 0x02, width: 8) 23 reserved 22 pattern 6 enable if set, pattern number is compared with incoming packets yes aw 0b0 21 pattern 5 enable yes aw 0b0 20 pattern 4 enable yes aw 0b0 19 pattern 3 enable yes aw 0b0 18 pattern 2 enable yes aw 0b0 17 pattern 1 enable yes aw 0b0 16 pattern 0 enable yes aw 0b0 wol control/status register (offset: 0x00, width: 16) 15 link change sta- tus set, if a link change wake up event oc- curred ne value 0 14 magic pattern status set, if a magic pattern wake up event oc- curred ne value 0 13 wake up frame status set, if a wake up frame wake up event occurred ne value 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 204 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 12 clear match result clears the magic pattern status and link change status bits in the wol control/status register and the match bits in the match result register . exec 0 11 enable pme on link change enable/disable pme on link change. executed, if appropriate bit is set to 1. if pme on link change is enabled and pme en in the pci power management control register is set, pme# on the pci bus is asserted on a successful pattern match in the link change unit. exec 0b10 0 10 disable pme on link change 0b01 1 9 enable pme on magic pattern enable/disable pme on magic pattern. executed, if appropriate bit is set to 1. if pme on magic pattern is enabled and pme en in the pci power management control register is set, pme# on the pci bus is asserted on a successful pattern match in the magic pattern unit. exec 0b10 0 8 disable pme on magic pattern 0b01 1 7 enable pme on wake up frame enable/disable pme on wake up frame. executed, if appropriate bit is set to 1. if pme on wake up frame is enabled and pme en in the pci power manage- ment control register is set, pme# on the pci bus is asserted on a successful pattern match in the wake up frame unit. exec 0b10 0 6 disable pme on wake up frame 0b01 1 5 enable link change unit enable/disable link change unit. executed, if appropriate bit is set to 1. if link change unit is enabled, on each link up event the link change status bit in the wol control/status register is set and depending on the pme set- tings pme# is asserted. exec 0b10 0 4 disable link change unit 0b01 1 3 enable magic pattern unit enable/disable magic pattern unit. executed, if appropriate bit is set to 1. if magic pattern unit is enabled, each incoming packet is compared to the amd magic pattern . if a pattern match occurs the corresponding magic pattern status bit in the wol control/status register is set and depending on the pme set- tings pme# is asserted. exec 0b10 0 2 disable magic pattern unit 0b01 1 bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 205 register description control register file 1 enable wake up frame unit enable/disable wake up frame unit. executed, if appropriate bit is set to 1. if wake up frame unit is enabled, each incoming packet is compared to each of the 7 wake up pattern stored in the pat- tern ram that has its corresponding pat- tern enable bit set. if a pattern match occurs the corresponding pattern match bit in the match result register is set and depending on the pme settings pme# is asserted. exec 0b10 0 0 disable wake up frame unit 0b01 1 reserved 31 reserved 30 reserved yes aw 0 29 reserved yes aw 0 28 reserved yes aw 0 27 reserved yes aw 0 26 reserved yes aw 0 25 reserved yes aw 0 24 reserved yes aw 0 pme match enab le register (offset: 0x0a, width: 8) 23 force pme generates a pme event exec 0 0 22 pme 6 enable if set, incoming packets that match with pattern number will generate a pme event. yes aw 0 21 pme 5 enable yes aw 0 20 pme 4 enable yes aw 0 19 pme 3 enable yes aw 0 18 pme 2 enable yes aw 0 17 pme 1 enable yes aw 0 16 pme 0 enable yes aw 0 mac address register high (offset: 0x08, width: 16) 15:8 mac<5> mac-address, byte 5 yes aw 0 7:0 mac<4> mac-address, byte 4 yes aw 0 bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 206 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications mac-address registers low (offset: 0x04, width: 32) 31:24 mac<3> mac-address, byte 3 yes aw 0 23:16 mac<2> mac-address, byte 2 yes aw 0 15:8 mac<1> mac-address, byte 1 yes aw 0 7:0 mac<0> mac-address, byte 0 yes aw 0 pattern read pointer register (offset: 0x0c, width: 7) 31:7 reserved 6:0 pattern read pointer address of the current 128 bit word in pattern ram to be compared, can be written for test purposes only yes, for test only value 0x00 pattern length register 0 (0 - 3) (offset: 0x10, width: 4 x 8) 31 reserved 30:24 pattern 3 length number of bytes - 1 to compare for pat- tern 3 when pattern length is 64 bytes then val- ue 63 is written to this register. minimum allowed pattern length is 6 bytes yes aw 0x00 23 reserved 22:16 pattern 2 length number of bytes - 1 to compare for pat- tern 2 when pattern length is 64 bytes then val- ue 63 is written to this register. minimum allowed pattern length is 6 bytes. yes aw 0x00 15 reserved 14:8 pattern 1 length number of bytes - 1 to compare for pat- tern 1 when pattern length is 64 bytes then val- ue 63 is written to this register. minimum allowed pattern length is 6 bytes. yes aw 0x00 7 reserved bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 207 register description control register file 6:0 pattern 0 length number of bytes - 1 to compare for pat- tern 0 when pattern length is 64 bytes then val- ue 63 is written to this register. minimum allowed pattern length is 6 bytes yes aw 0x00 pattern length register 1 (4 - 6) (offset: 0x14, width: 3 x 8) 31:23 reserved 22:16 pattern 6 length number of bytes - 1 to compare for pat- tern 6 when pattern length is 64 bytes then val- ue 63 is written to this register. minimum allowed pattern length is 6 bytes yes aw 0x00 15 reserved 14:8 pattern 5 length number of bytes - 1 to compare for pat- tern 5. when pattern length is 64 bytes then val- ue 63 is written to this register. minimum allowed pattern length is 6 bytes yes aw 0x00 7 reserved 6:0 pattern 4 length number of bytes - 1 to compare for pat- tern 4 when pattern length is 64 bytes then val- ue 63 is written to this register. minimum allowed pattern length is 6 bytes yes aw 0x00 pattern counter register 0 (0 - 3) (offset: 0x18, width: 4 x 8) 31 reserved 30:24 pattern 3 counter current byte to compare for pattern 3 to value 0x00 23 reserved 22:16 pattern 2 counter current byte to compare for pattern 2 to value 0x00 15 reserved 14:8 pattern 1 counter current byte to compare for pattern 1 to value 0x00 7 reserved bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 208 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.58 pattern ram address: 0x1000 - 0x13fc (link 1) width [bit]:256 x 32 bit for accesses to the pattern ram the wol pattern matching must be disabled before (set bits 1:0 of wol control register to 0b01 (inactive)). the pattern ram is fully mapped into the i/o space and occupies 256 consecutive 32 bit words. during read ac- cesses data is read directly from ram and no special sequence is needed. for write accesses the four 32 bit dwords of a 128 bit ram word are collected in a 128 bit register and the write access to the uppermost dword (ad- dress: 0x0c, 0x1c,...) causes the regi ster contents to be written into the ram. therefore the lower three dwords have to be written first. the pattern ram co ntents are undetermined after power on. 6:0 pattern 0 counter current byte to compare for pattern 0 to value 0x00 pattern counter register 1 (4 - 6) (offset: 0x1c, width: 3 x 8) 31:23 reserved 22:16 pattern 6 counter current byte to compare for pattern 6 to value 0x00 15 reserved 14:8 pattern 5 counter current byte to compare for pattern 5 to value 0x00 7 reserved 6:0 pattern 4 counter current byte to compare for pattern 4 to value 0x00 bit name description write read reset (none) pattern ram 31:0 lower half qword no. 0 (offset: 0x00, width: 32 bit) read reads ram directly, write writes only intermediate register yes aw 0bxxxx xxxx 31:0 upper half qword no. 0 (offset: 0x04, width: 32 bit) read reads ram directly, write writes only intermediate register yes aw 0bxxxx xxxx 31:0 lower half qword no. 1 (offset: 0x08, width: 32 bit) read reads ram directly, write writes only intermediate register yes aw 0bxxxx xxxx bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 209 register description control register file 3.3.2.59 tcp segmentati on header registers there are four sets of 34 tcp segmentation header registers: tcp segmentation header registers: address: 0x1900 - 0x1984 (asynchronous) width [bit]: 34 x 32 all sets of header registers have the same structure. all registers are written and read by the tcp segmentation logic automatically. they can be accessed (read/write) through ytb for debug purposes. 31:0 upper half qword no. 1 (offset: 0x0c, width: 32 bit) read reads ram directly, write triggers write of 128 bit in ram yes aw 0bxxxx xxxx ... 31:0 lower half qword no. 126 (offset: 0x3f0, width: 32 bit) read reads ram directly, write writes only intermediate register yes aw 0bxxxx xxxx 31:0 upper half qword no. 126 (offset: 0x3f4, width: 32 bit) read reads ram directly, write writes only intermediate register yes aw 0bxxxx xxxx 31:0 lower half qword no. 127 (offset: 0x3f8, width: 32 bit) read reads ram directly, write writes only intermediate register yes aw 0bxxxx xxxx 31:0 upper half qword no. 127 (offset: 0x3fc, width: 32 bit) read reads ram directly, write triggers write of 128 bit in ram yes aw 0bxxxx xxxx bit name description write read reset (link) tcp segmentation header register 0 lo (offset: 0x00 width: 32) 31:0 mac_hdr_0 word 0/1 of mac header yes value 0x0 tcp segmentation header register 0 hi (offset: 0x04 width: 32) 31:0 mac_hdr_1 word 2/3 of mac header yes value 0x0 tcp segmentation header register 1 lo (offset: 0x08 width: 32) 31:0 mac_hdr_2 word 4/5 of mac header yes value 0x0 bit name description write read reset (none) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 210 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications tcp segmentation header register 1 hi (offset: 0x0c width: 32) 31:16 ip_hdr_0 word 0 of ip header yes value 0x0 15:0 mac_hdr_3 word 6 of mac header yes value 0x0 tcp segmentation header register 2 lo (offset: 0x10 width: 32) 31:0 ip_hdr_1 word 1/2 of ip header yes value 0x0 tcp segmentation header register 2 hi (offset: 0x14 width: 32) 31:0 ip_hdr_2 word 3/4 of ip header yes value 0x0 tcp segmentation header register 3 lo (offset: 0x18 width: 32) 31:0 ip_hdr_3 word 5/6 of ip header yes value 0x0 tcp segmentation header register 3 hi (offset: 0x1c width: 32) 31:0 ip_hdr_4 word 7/8 of ip header yes value 0x0 tcp segmentation header register 4 lo (offset: 0x20 width: 32) 31:16 ip_opt_0 word 0 of ip header options 1 yes value 0x0 15:0 ip_hdr_5 word 9 of ip header yes value 0x0 tcp segmentation header register 4 hi (offset: 0x24 width: 32) 31:0 ip_opt_1 word 1/2 of ip header options yes value 0x0 tcp segmentation header register 5 lo (offset: 0x28 width: 32) 31:0 ip_opt_2 word 3/4 of ip header options yes value 0x0 tcp segmentation header register 5 hi (offset: 0x2c width: 32) 31:0 ip_opt_3 word 5/6 of ip header options yes value 0x0 tcp segmentation header register 6 lo (offset: 0x30 width: 32) 31:0 ip_opt_4 word 7/8 of ip header options yes value 0x0 tcp segmentation header register 6 hi (offset: 0x34 width: 32) 31:0 ip_opt_5 word 9/10 of ip header options yes value 0x0 tcp segmentation header register 7 lo (offset: 0x38 width: 32) 31:0 ip_opt_6 word 11/12 of ip header options yes value 0x0 tcp segmentation header register 7 hi (offset: 0x3c width: 32) 31:0 ip_opt_7 word 13/14 of ip header options yes value 0x0 bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifica tion: proprietary information page 211 register description control register file tcp segmentation header register 8 lo (offset: 0x40 width: 32) 31:0 ip_opt_8 word 15/16 of ip header options yes value 0x0 tcp segmentation header register 8 hi (offset: 0x44 width: 32) 31:0 ip_opt_9 word 17/18 of ip header options yes value 0x0 tcp segmentation header register 9 lo (offset: 0x48 width: 32) 31:16 tcp_hdr_0 word 0 of tcp header yes value 0x0 15:0 ip_opt_10 word 19 of ip header options yes value 0x0 tcp segmentation header register 9 hi (offset: 0x4c width: 32) 31:0 tcp_hdr_1 word 1/2 of tcp header yes value 0x0 tcp segmentation header register 10 lo (offset: 0x50 width: 32) 31:0 tcp_hdr_2 word 3/4 of tcp header yes value 0x0 tcp segmentation header register 10 hi (offset: 0x54 width: 32) 31:0 tcp_hdr_3 word 5/6 of tcp header yes value 0x0 tcp segmentation header register 11 lo (offset: 0x58 width: 32) 31:0 tcp_hdr_4 word 7/8 of tcp header yes value 0x0 tcp segmentation header register 11 hi (offset: 0x5c width: 32) 31:16 tcp_opt_0 word 0 of tcp header options 2 yes value 0x0 15:0 tcp_hdr_5 word 9 of tcp header yes value 0x0 tcp segmentation header register 12 lo (offset: 0x60 width: 32) 31:0 tcp_opt_1 word 1/2 of tcp header options yes value 0x0 tcp segmentation header register 12 hi (offset: 0x64 width: 32) 31:0 tcp_opt_2 word 3/4 of tcp header options yes value 0x0 tcp segmentation header register 13 lo (offset: 0x68 width: 32) 31:0 tcp_opt_3 word 5/6 of tcp header options yes value 0x0 tcp segmentation header register 13 hi (offset: 0x6c width: 32) 31:0 tcp_opt_4 word 7/8 of tcp header options yes value 0x0 tcp segmentation header register 14 lo (offset: 0x70 width: 32) 31:0 tcp_opt_5 word 9/10 of tcp header options yes value 0x0 bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 212 document classification: proprie tary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 3.3.2.60 pci configur ation register file address: 0x1c00 - 0x1efc the whole configuration register file is made accessible within this address area of the control register file. it is read only with some exceptions: our register 1 and 2 and vpd address and vpd data register may be written. write operations are completed normally on the bus and the data is discarded. for testing purposes, the configuration register file may be set writable by en config write . tcp segmentation header register 14 hi (offset: 0x74 width: 32) 31:0 tcp_opt_6 word 11/12 of tcp header options yes value 0x0 tcp segmentation header register 15 lo (offset: 0x78 width: 32) 31:0 tcp_opt_7 word 13/14 of tcp header options yes value 0x0 tcp segmentation header register 15 hi (offset: 0x7c width: 32) 31:0 tcp_opt_8 word 15/16 of tcp header options yes value 0x0 tcp segmentation header register 16 lo (offset: 0x80 width: 32) 31:0 tcp_opt_9 word 17/18 of tcp header options yes value 0x0 tcp segmentation header register 16 hi (offset: 0x84 width: 32) 31:16 reserved 0x0 0x0 0x0 15:0 tcp_opt_10 word 19 of tcp header options yes value 0x0 1. the ip header option registers are optional. if the ip header options don?t exist at all or only partially exist, the tcp header register s and tcp header option registers move up accordingly. 2. the tcp header option registers are optio nal. if the tcp header options don?t exist at all or only partially exist, the unused tcp header option registers are undefined. bit name description write read reset (link) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 213 gmac registers 3.4 gmac registers all gmac registers are mapped into a subsequent range on 32-bit word boundaries. the gmac interface imple- ments write posting and delayed transactions on read ac cesses. target reads are retried until the addressed reg- ister is synchronized to pci clock. the gmac?s node proce ssor interface is running in 16-bit mode. the offset of the register addresses in the pci address space is calculat ed by multiplying the 16-b it xmac register addresses by 2. the gmac registers can be accessed with any width at dword boundaries. on the pci side all accesses to the gmac are completed normally. mac receive status word receive status word: 3.4.1 mac register definitions the registers in the 88E8053 device are accessible thro ugh the cpu interface. th e smi (serial management interface) control register, smi data register, and the phy address register are used to read from and write to registers in the phy. bit(s) description 31:16 byte count, this field provides byte count of received packet 15:14 reserved 13 vlan packet 12 jabber (a packet that is too long and has a crc error) 11 undersize packet (a packet which is less than 64 bytes, but with a good crc) 10 multicast packet 9 broadcast packet 8 receive ok (good packet) 7 good flow control packet 6 bad flow control packet 5 mii error 4 oversize (packet longer than max. length with good crc) 3 fragment 2reserved 1 crc error 0 receive fifo overflow marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 214 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table 29: general purpose status register (gpsr) offset: 0x2800 (all valid bits in this register are read-only) bits field type/ reset value description 15 speed read port speed this bit is read-only. 0 - 10 mbps 1 - 100 mbps (only valid if gigspeed bit is 0) write reset 1 14 duplex read port duplex mode this bit is read-only. 0 - half duplex 1 - full duplex write reset 0 13 fctltx read transmit flow control mode this bit is read-only. 0 - flow control mode enabled 1 - flow control mode disabled write reset 0 12 link read link status this bit is read-only. 0 - link is down 1 - link is up write reset 1 11 pause read port is in "flow control disabled" state, i.e. the transmit state machine is in pause state. this bit is set when an ieee 802.3x flow-control pause (xoff) packet is received (and flow-control is enabled and the port is in full-duplex mode). reset when xon is received, or when the xoff timer has expired. this bit is read-only. write reset 0 10 txinprog read tx in progress indicates that the port?s transmitter is in an active transmission state. this bit is read-only. write reset 0 9 excesscol read excessive collisions occurred indicates that a packet transmission experienced 16 collisions. write reset 0 8 latecol read late collision occurred a collision occurred beyond 64-bit-times from start of the packet. write reset 0 7:6 reserved read write reset 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 215 gmac registers 5miiphystc read mii phy status change indicates a status change reported by the phy connected to this port. set, when the mii management interface block identi- fies a change in phy?s register 1. write reset 0 4 gigspeed read this bit is only valid if bit 15 (speed) is set. 0 - follow the speed bit setting 1 - 1000mbps operation mode write reset 1 3 partition read partition mode indicates that the mac has entered the partition mode. when in this mode, the port transmits pending packets, ignoring the colli- sions. write reset 0 2fctlrx read receive flow control mode this bit is read-only. 0 - flow-control mode enabled. 1 - flow-control mode disabled. write reset 0 1 promiscuous mode read this bit is set if the device is in promiscuous mode. this bit will be set to 1 at power up. write reset 0 0reserved read reserved write reset 0 table 30: general purpose control register (gpcr) offset: 0x2804 bits field type/ reset value description 15:14 reserved read write reset 13 fctltx read transmit flow control mode 0 - enable ieee 802.3x flow control 1 - disable ieee 802.3x flow control note: valid only if auto-negotiation for flow control is disabled. write reset table 29: general purpose status register (gpsr) offset: 0x2800 (all valid bits in this register are read-only) bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 216 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 12 txen read transmit enable 0 - disabled 1 - enable ethernet port is ready to transmit. write reset 0 11 rxen read receive enable 0 - disabled 1 - enable ethernet port is ready to receive. write reset 0 10 reserved read write reset 9lpbk read loopback mode 0 - normal mode 1 - internal loopback mode tx data is looped back to the rx lines and also transmitted to the mii interface pins. write reset 0 8par read partition enable when more than 61 collisions occur while transmitting, the port enters partition mode. it waits for the first good packet from the wire, and then goes back to normal mode. in partition mode it continues transmitting, but it does not receive. 0 - normal mode 1 - partition mode write reset 0 7 gigspeed read gigspeed 0 - follow the speed bit setting 1 - 1000mbps (only valid if speed bit (3) is set to 1). write reset 1 6flp read force link pass 1 - force link pass 0 - do not force link pass write reset 1 5hd read duplex mode 0 - half duplex 1 - full duplex note: valid only, if auto-negotiation for duplex mode is dis- abled. write reset 0 table 30: general purpose control register (gpcr) offset: 0x2804 bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 217 gmac registers 4fctlrx read receive flow control mode 0 - enable ieee 802.3x flow control 1 - disable ieee 802.3x flow control note: valid only, if auto-update for flow control is disabled. write reset 0 3 speed read port speed 0 - 10mbps 1 - 100mbps (and gigspeed is set to 0) note: valid only, if speed en bit is set. write reset 1 2dplyxen read enable auto-update for duplex mode 0 - enable 1 - disable write reset 0 1fctlen read enable auto-update for 802.3x flow control 0 - enable 1 - disable write reset 1 0 speeden read enable auto-update for speed 0 - enable 1 - disable write reset 0 table 31: transmit control register (tcr) offset: 0x2808 bits field type/ reset value description 15 fj read force jam / flow control when in half-duplex mode, the cpu uses this bit to force colli- sions on the ethernet segment. when the cpu recognizes that it is going to run out of receive buffers, it can force the transmit- ter to send jam frames, forcing collisions on the wire. the cpu must clear the fj bit when more resources are available in order to allow transmission on the ethernet segment. when in full-duplex mode and if flow control is enabled, this bit causes the port?s transmitter to send flow control pause pack- ets. the cpu should reset this bit when more resources are available. write reset 0 table 30: general purpose control register (gpcr) offset: 0x2804 bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 218 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 14 crcd read insert crc 0 - enable 1 - disable insertion of crc in transmit packets when this bit is set, the mac does not insert a crc at the end of a transmit packet. write reset 0 13 padd read pad packets 0 - enable 1 - disable padding of packets of length less than 64 bytes when this bit is set, the mac does not add padding to packets which are smaller than 64 bytes. write reset 0 12:10 colth read collision threshold for fast ethernet: number of tx clocks to count from the begin- ning of a packet before a collision is counted as a late collision. the number is in 32 cycle multiples (16 bytes transmit time). for gigabit ethernet: the number is fixed to 512 bytes. write reset 100 (64 bytes) 9:8 reserved read 0 reserved write 0 reset 0 7:0 padding pattern read 00 when padding is enabled, these bits will allow to change pad- ding patterns in ?byte?. for short packet padding. this pattern is programmable by this register.value in this will be used as ?one byte? repetitions in the padding. example, if you program ?aa?, required 16 bytes padding will look like ?aa aa?. write 00 reset table 31: transmit control register (tcr) offset: 0x2808 bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 219 gmac registers table 32: receive control register (rcr) offset: 0x280c bits field type/ reset value description 15 unfien read unicast filter enable 0 - disable 1 - enable by setting this bit, the mac will only pass packets with da that matches either sa1 or sa2 on unicast packets. if only one address needs to be matched, the same address should be written in both sa1 and sa2. write reset 0 14 mufien read multicast filter enable 0 - disable 1 - enable when this bit is set, mac passes multicast packets to the dma which have a da. produces a hit with the hash mechanism. macah1, macah2, macah3, and macah4 form the hash register. macah1 represents the least significant bits of hash register and macah4 the most significant bits. possible modes: bit 15 : bit 14 0 0 - promiscuous mode 0 1 - multicast filtering enabled 1 0 - unicast filtering enabled 1 1 - both unicast and multicast filtering enabled write reset 0 13 crcr read remove crc 0 - keep crc 1- remove crc remove crc from receive packets. the 4-byte crc is removed from the received packets if this bit is set. write reset 0 12 passfc read pass flow control packets 0 - drop fc packets and do not send to fifo 1 - pass fc packets to fifo note: only real packet is dropped, da and sa of the fc packet are still passed in drop fc packets mode. write reset 11:0 reserved read reserved write reset 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 220 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table 33: transmit flow control register (tfcr) offset: 0x2810 bits field type/ reset value description 15:0 pausetime read indicates the number of slot times during which the remote port receiving a flow-control packet from this port cannot send pack- ets. this field is inserted into the transmitted flow control pack- ets. write reset 0xffff table 34: transmit parameter register (tpr) offset: 0x2814 bits f ie ld type/ reset value description 15:14 jam_len read two bits to determine the jam length (in backpressure) as fol- lows: 00 = 12k bit times for fe 00 = 24k bit times for gig 01 = 24k bit times for fe 01 = 48k bit times for gig 10 = 32k bit times for fe 10 = 64k bit times for gig 11 = 48k bit times for fe 11 = 96k bit times for gig these values are only true when there is no data on the fifo bus. if there is data, this data will be sent. write reset 11 (48k bit time in fe mode 96k bit times in gig mode) 13:9 jam_ipg read jam inter packet gap for fast ethernet: 13:9 these bits determine the jam ipg. the step is four bit times. the jam ipg varies between 8-bit times and 124. for gig: 11:9 = 011 010 - 32 bit times 011 - 48 bit times (default mode) 100 - 64 bit times 101 - 80 bit times 110 - 96 bit times 111 - 112 bit times note: this value should be between above specified values only. write reset 01011 (44 bit times in fe mode 48 bit times in gig mode) marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 221 gmac registers 8:4 ipgjam2data read inter packet jam data for fast ethernet: 8:4 these bits determine the ipg jam to data. the step is four bit times. the value varies between 8 bit times and 124. for gig: 6:4 = 100 010 - 32 bit times 011 - 48 bit times 100 - 64 bit times (default mode) 101 - 80 bit times 110 - 96 bit times 111 - 112 bit times note: this value should be between above specified values only. write reset 11100 (112 bit times for fe) 64 bit times for gig 3:0 back-off limit read these register bits set the back-off limit. these values are only valid if limit4 in the smr register is set. write reset 0100 table 35: serial mode register (smr) offset: 0x2818 bits field type/ reset value description 15:14 reserved read reserved write reset 0 13:11 data blinder read the number of nibbles from the beginning of the ipg, in which the ipg counter is restarted when detecting a carrier activity. following this value, the port enters the data blinder zone and does not reset the ipg counter. this ensures fair access to the medium. value should be written in hex format. the step is 4-bit time. note: these bits should only be changed at the start up or ini- tialization and port is disabled. write reset 00100 table 34: transmit parameter register (tpr) offset: 0x2814 bits f i el d type/ reset value description marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 222 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 10 limit4 read limit4 the number of consecutive packet collisions that occurs before the collision counter is reset. 0 - the port resets its collision counter after 16 consecutive retransmit trials and restarts the back off algorithm. 1- the port resets its collision counter and restarts the backoff algorithm after 4 consecutive transmit trials. write reset 0 9:8 vlan_en, mfl read vlan enabled, maximum frame length 00 - max. frame length = 1518 10 - max. frame length = 1522 01 - max. frame length = 9018 11 - max. frame length = 9022 write reset 00 7:5 reserved read reserved write reset 0 4:0 ipgdata read inter packet gap data for fast ethernet: 4:0 inter-packet gap (ipg): the step is 4 bit times. the value may vary between 48 bit times to 124. note: these bits can only be changed when the ethernet port is disabled. for gig: 2:0 write reset 11000 (96 bit time) table 36: source address low (sal1) offset: 0x281c bits field type/ reset value description 15:0 sa1 [15:0] read source address the least significant bits of the source address for the port. this address is used for flow control. write reset 0 table 35: serial mode register (smr) offset: 0x2818 bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 223 gmac registers table 37: source address middle (sam1) offset: 0x2820 bits field type/ reset value description 15:0 sa1 [31:16] read source address the middle bits of the source address for the port. this address is used for flow control. write reset 0 table 38: source address high (sa1h) offset: 0x2824 bits field type/ reset value description 15:0 sa1 [47:32] read source address the most significant 16 bits of the source address for the port. this address is used for flow control. write reset 0 table 39: source address low (sal2) offset: 0x2828 bits field type/ reset value description 15:0 sa2 [15:0] read source address used for vlan and others. the least significant bits of the source address for the port. write reset 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 224 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table 40: source address middle (sam2) offset: 0x282c bits field type/ reset value description 15:0 sa2 [31:16] read source address used for vlan and others. the middle bits of the source address for the port. write reset 0 table 41: source address high (sah2) offset: 0x2830 bits field type/ reset value description 15:0 sa 2[47:32] read source address used for vlan and others. the most significant 16 bits of the source address for the port. write reset 0 table 42: multicast addres s hash register 1 (mcah1) offset: 0x2834 bits field type/ reset value description 15:0 mcah1[15:0] read multicast address hash register 1 write reset 0 table 43: multicast addres s hash register 2 (mcah2) offset: 0x2838 bits field type/ reset value description 15:0 mcah2[15:0] read multicast address hash register 2 write reset 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 225 gmac registers table 44: multicast address hash register 3 (mcah3) offset: 0x283c bits field type/ reset value description 15:0 mcah3[15:0] read multicast address hash register 3 write reset 0 table 45: multicast address hash register 4 (mcah4) offset: 0x2840 bits field type/ reset value description 15:0 mcah4[15:0] read multicast address hash register 4 write reset 0 table 46: transmit interrupt register (tir) offset: 0x2844 bits field type/ reset value description 15:0 tir[15:0] read transmit overflow interrupt register 0x70 to 0x8f of mib counters. write reset 0 transmit interrupt register definitions 15 late read yes the number of times a collision is detected later than 512-times into the transmission of a packet. write no reset 14 collisions read yes the number of collisions experienced by a port during packet transmission. write no reset marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 226 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 13 spare read yes write no reset 12 outmaxoctets read yes the number of packets transmitted that were between 1519 and max_len bytes in length inclusive. write no reset 11 out1518octets read yes the number of packets transmitted that were between 1024 and 1518 bytes in length inclusive. write no reset 10 out1023octets read yes the number of packets transmitted that were between 512 and 1023 bytes in length inclusive. write no reset 9 out511octets read yes the number of packets transmitted that were between 256 and 511 bytes in length inclusive. write no reset 8 out255octets read yes the number of packets transmitted that were between 128 and 255 bytes in length inclusive. write no reset 7 out127octets read yes the number of packets transmitted that were between 65 and 127 bytes in length inclusive. write no reset 6 out64octets read yes the number of packets transmitted that were 64 bytes in length. write no reset 5:4 outoctets read yes the number of bytes of data transmitted, including bad packets. the count includes the fcs but not the preamble write no reset table 46: transmit interrupt register (tir) offset: 0x2844 bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 227 gmac registers 3 outmulticasts read yes the number of multicast packets transmitted by the port. write no reset 2 outpause read yes the number of pause packets transmitted by the port write no reset 1 outbroadcasts read yes the number of broadcast packets transmitted by the port. write no reset 0outunicasts read yes the number of unicast packets transmitted by the port. write no reset table 47: receive interrupt register (rir) offset: 0x2848 bits field type/ reset value description 15:0 rir[15:0] read receive overflow interrupt register 0x40 to 0x5f of mib counters write reset 0 receive interrupt register definitions 15 in511octets read yes the number of packets (including bad packets) received that were between 256 and 511 bytes in length inclusive. write no reset 14 in255octets read yes the number of packets (including bad packets) received that were between 128 and 255 bytes in length inclusive. write no reset table 46: transmit interrupt register (tir) offset: 0x2844 bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 228 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 13 in127octets read yes the number of packets (including bad packets) received that were between 65 and 127 bytes in length inclusive. write no reset 12 in64octets read yes the number of packets (including bad packets) received that were 64 bytes in length. write no reset 11 fragments read yes the number of packets received by the port that are less than 64 bytes in long and have fcs error. write no reset 10 undersize read yes the number of good packets received by the port that are less than 64 bytes long. write no reset 9:8 inbadoctets read yes the number of bytes of data received in bad packets. the count includes the fcs but not the preamble. write no reset 7:6 ingoodoctets read yes the number of good bytes of data received. the count includes the fcs but not the preamble. write no reset 5spare read yes write no reset 4infcserr read yes the number of packets that have a bad fcs. write no reset 3 inmulticasts read yes the number of good multicast packets received by the port. write no reset table 47: receive interrupt register (rir) offset: 0x2848 bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 229 gmac registers 2 inpause read yes the number of pause packets received by the port. write no reset 1 inbroadcasts read yes the number of good broadcast packets received by the port. write no reset 0 inunicasts read yes the number of good unicast packets received by the port. write no reset table 47: receive interrupt register (rir) offset: 0x2848 bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 230 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table 48: transmit and receive interrupt register (tir_rir) offset: 0x284c bits field type/ reset value description 15:0 tir_rir[15:0] read 7:0 - receive overflow interrupt register msbs 0x60 to 0x6f of mib counters 11:8 - transmit overflow interrupt register msbs 0x90 to 0x97 of mib counters write reset 0 transmit and receive interrupt register definitions 15:12 reserved read write reset 11 underflow read yes the number of multicast packets transmitted by the port. the number of times a underflow condition occurs in the transmit fifo. write no reset 10 single read yes the number of successfully transmitted packets that experi- enced exactly one collision. write no reset 9 multiple read yes the number of broadcast packets transmitted by the port. the number of successfully transmitted packets that experi- enced more than one collision. write no reset 8 excessive read yes the number of packets that are not transmitted from a port because the packet experienced 16 transmission attempts. write no reset 7spare read yes write no reset 6overflow read yes the number of times the overflow condition occurs. write no reset 5spare read yes write no reset marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 231 gmac registers 4 jabber read yes the number of packets received that were longer than max_len bytes, and has a fcs error. write no reset 3oversize read yes the number of packets received that are longer than max_len bytes that were otherwise well formed. write no reset 2inmaxoctets read yes the number of packets (including bad packets) received that were between 1519 and max_len bytes in length inclusive. write no reset 1 in1518octets read yes the number of packets (including bad packets) received that were between 1024 and 1518 bytes in length inclusive. write no reset 0 in1023octets read yes the number of packets (including bad packets) received that were between 512 and 1023 bytes in length inclusive. write no reset table 48: transmit and receive interrupt register (tir_rir) offset: 0x284c bits field type/ reset value description marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 232 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table 49: transmit interrupt mask register (timr) offset: 0x2850 bits field type/ reset value description 15:0 timr[15:0] read transmit overflow interrupt register 0 - pass 1 - mask write reset 0 table 50: receive interrupt mask register (rimr) offset: 0x2854 bits field type/ reset value description 15:0 rimr[15:0] read receive overflow interrupt register 0 - pass 1 - mask write reset 0 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 233 gmac registers table 51: transmit and receive interrupt mask register (timr_rimr) offset: 0x2858 bits field type/ reset value description 15:0 timr_rimr [15:0] read 7:0 - receive overflow interrupt register msbs 11:8 transmit overflow msbs 0 - pass 1 - mask write reset table 52: smi control register (smicr) offset: 0x2880 bits field type/ reset value description 15:11 phyad read phy device address write reset 0 10:6 regad read phy device register address write reset 0 5 opcode read opcode 0 ? write 1 ? read write reset 0 4 readvalid read read valid indicates that the read operation has been completed for the addressed (regad) register, and the data is valid in the smi data register. read only. write reset 0 3busy read busy 0 - smi interface is available 1 - indicates that an operation is in progress and that cpu must not write to the smi registers at this time. read only. write reset 0 2:0 reserved read write reset 0 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 234 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table 53: smi data register (smidr) offset: 0x2884 bits field type/ reset value description 15:0 data read smi read operation two transactions are required: (1) write to the smi control register (smicr) with opcode = 1 and phyad, regad pointing to the phy register to be read. (2) read from the smi data register (smidr). this read should be performed when the read valid bit in smicr is set. the data remains undefined as long as read valid is 0. smi write operation two transactions are required: (1) write the register data to be written into the phy register in the smi data register (smidr). (2) write to the smi control register (smicr) with opcode = 0 and phyad, regad pointing to the phy register to be written to. write reset 0 table 54: phy address register (par) offset: 0x2888 bits field type/ reset value description 15:6 reserved read write reset 0 5mibclrmode read mib counters clear mode setting this bit causes the counters to reset when the cpu reads a counter. in order to reset all mib counters, the cpu should set this bit and read all the counters individually. the reset is only performed when the lower 16 bits of the counters are read and if mibclrmode is set. write reset 0 4 loadtstcnt read load a count of ffff_fff0 into the rmon counters when it is read. this is used only in test mode. write reset 000 3:0 reserved read write reset marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 235 gmac registers mib counters address in control register file field bits description 0x2900 inunicasts 15:0 the number of good unicast packets received by the port. 0x2904 inunicasts 31:16 0x2908 inbroadcasts 15:0 the number of good broadcast packets received by the port. 0x290c inbroadcasts 31:16 0x2910 in pause 15:0 the number of pause packets received by the port. 0x2914 inpause 31:16 0x2918 inmulticasts 15:0 the number of good multicast packets received by the port. 0x291c inmulticasts 31:16 0x2920 infcserr 15:0 the number of packets that have a bad fcs. 0x2924 infcserr 31:16 0x2928 spare 0x292c spare 0x2930 ingoodoctets 15:0 the number of good bytes of data received. the count includes the fcs but not the preamble. 0x2934 ingoodoctets 31:16 0x2938 ingoodoctets 47:32 0x293c ingoodoctets 63:48 0x2940 inbadoctets 15:0 the number of bytes of data received in bad packets. the count includes the fcs but not the preamble. 0x2944 inbadoctets 31:16 0x2948 inbadoctets 47:32 0x294c inbadoctets 63:48 0x2950 undersize 15:0 the number of good packets received by the port are less than 64 bytes long. 0x2954 undersize 31:16 0x2958 fragments 15:0 the number of packets received by the port that are less than 64 bytes long and have a fcs error. 0x295c fragments 31:16 marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 236 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 0x2960 in64octets 15:0 the number of packets (including bad packets) received that were 64 bytes in length. 0x2964 in64octets 31:16 0x2968 in127octets 15:0 the number of packets (including bad packets) received that were between 65 and 127 bytes in length. 0x296c in127octets 31:16 0x2970 in255octets 15:0 the number of packets (including bad packets) received that were between 128 and 255 bytes in length. 0x2974 in255octets 31:16 0x2978 in511octets 15:0 the number of packets (including bad packets) received that were between 256 and 511 bytes in length. 0x297c in511octets 31:16 0x2980 in1023octets 15:0 the number of packets (including bad packets) received that were between 512 and 1023 bytes in length. 0x2984 in1023octets 31:16 0x2988 in1518octets 15:0 the number of packets (including bad packets) received that were between 1024 and 1518 bytes in length. 0x298c in 1518octets 31:16 0x2990 inmaxoctets 15:0 the number of packets (including bad packets) received that were between 1519 and max_len bytes in length. 0x2994 inmaxoctets 31:16 0x2998 oversize 15:0 the number of packets received that are longer than max_len bytes and were well formed. 0x299c oversize 31:16 0x29a0 jabber 15:0 the number of packets received that were longer than max_len and had an fcs error. 0x29a4 jabber 31:16 0x29a8 spare 0x29ac spare 0x29b0 overflow 15:0 the number of times the overflow condition occurs. 0x29b4 overflow 31:16 0x29b8 spare 0x29bc spare address in control register file field bits description marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 237 gmac registers 0x29c0 outunicasts 15:0 the number of unicast packets transmitted by the port. 0x29c4 outunicasts 31:16 0x29c8 outbroadcasts 15:0 the number of broadcast packets transmitted by the port. 0x29cc outbroadcasts 31:16 0x29d0 outpause 15:0 the number of pause packets transmitted by the port. 0x29d4 outpause 31:16 0x29d8 outmulticasts 15:0 the number of good multicast packets transmitted by the port. 0x29dc outmulticasts 31:16 0x29e0 outoctets 15:0 the number of bytes of data transmitted, including bad packets. the count includes fcs but not the preamble. 0x29e4 outoctets 31:16 0x29e8 outoctets 47:32 0x29ec outoctets 63:48 0x29f0 out64octets 15:0 the number of packets (including bad packets) transmit- ted that were 64 bytes in length. 0x29f4 out64octets 31:16 0x29f8 out127octets 15:0 the number of packets (including bad packets) transmit- ted that were between 65 and 127 bytes in length. 0x29fc out127octets 31:16 0x2a00 out255octets 15:0 the number of packets (including bad packets) transmit- ted that were between 128 and 255 bytes in length. 0x2a04 out255octets 31:16 0x2a08 out511octets 15:0 the number of packets (including bad packets) transmit- ted that were between 256 and 511 bytes in length. 0x2a0c out511octets 31:16 0x2a10 out1023octets 15:0 the number of packets (including bad packets) transmit- ted that were between 512 and 1023 bytes in length. 0x2a14 out1023octets 31:16 0x2a18 out1518octets 15:0 the number of packets (including bad packets) transmit- ted that were between 1024 and 1518 bytes in length. 0x2a1c out 1518octets 31:16 address in control register file field bits description marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 238 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications 0x2a20 outmaxoctets 15:0 the number of packets (including bad packets) transmit- ted that were between 1519 and max_len bytes in length. 0x2a24 outmaxoctets 31:16 0x2a28 spare 0x2a2c spare 0x2a30 collisions 15:0 the number of collisions experienced by a port during packet transmission. 0x2a34 collisions 31:16 0x2a38 late 15:0 the number of times that a collision is detected later than 512 bit-times into the transmission of a packet. 0x2a3c late 31:16 0x2a40 excessive 15:0 the number of packets that are not transmitted from a port because the packet experienced 16 transmission attempts. 0x2a44 excessive 31:16 0x2a48 multiple 15:0 the number of successfully transmitted packets that experienced more than one collision. 0x2a4c multiple 31:16 0x2a50 single 15:0 the number of successfully transmitted packets that experienced exactly one collision. 0x2a54 single 31:16 0x2a58 underflow 15:0 the number of times an underflow condition occurs in the transmit fifo. 0x2a5c underflow 31:16 address in control register file field bits description marvell confidential - for dfi only free datasheet http:///
electrical specifications absolute maximum ratings copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 239 section 4. electrical specifications 4.1 absolute maximum ratings stresses above those listed in absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliabil- ity. symbol parameter min typ max units v dd(3.3) power supply voltage on a vddh with respect to v ss -0.5 +3.6 v v dd(2.5) power supply voltage on v ddo_ttl with respect to vss -0.5 +3.6 or v dd(3.3) +0.5 1 whichever is less 1. vdd(2.5) must never be more than 0.5v greater than vdd( 3.3) or damage will result. this implies that power must be applied to vdd(3.3) before or at the same time as vdd(2.5). v v dd(1.2) power supply voltage on v dd with respect to v ss -0.5 +3.6 or v dd(2.5) +0.5 2 whichever is less 2. vdd(1.2) must never be more than 0.5v greater than vdd( 2.5) or damage will result. this implies that power must be applied to vdd(2.5) before or at the same time as vdd(1.2). v v pin voltage applied to any input pin with respect to v ss -0.5 +3.6 or v ddo +0.5 3 whichever is less 3. vpin must never be more than 0.5v greater than vddo or damage will result. v t storage storage temperature -55 +125 4 4. 125 c is the re-bake temperature. for extended storage time greater than 24 hours, +85 c should be the maxi- mum. c marvell confidential - for dfi only free datasheet http:///
yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 240 document classification: proprie tary information april 20, 2004, advanced 4.2 recommended operating conditions symbol parameter condition min typ max units v dd(3.3) 3.3v power supply for pins v ddo_ttl 3.135 3.3 3.465 v v dd(2.5) 2.5v power supply for pins a vddl 2.375 2.5 2.625 v v dd(1.2) 1.2v power supply for pins v dd 1.140 1.2 1.260 v t a ambient operating temperature 070 c t j maximum junction temperature 125 1 1. refer to white paper on tj thermal calculations for more information. c rset internal bias reference constant voltage reference. external 4.99 k ? 1% resistor connection to vss. 2465 2490 2515 ? marvell confidential - for dfi only free datasheet http:///
electrical specifications package thermal information copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 241 4.3 package thermal information 4.3.1 thermal conditions for 64-pin qfn package symbol parameter condition min typ max units ja thermal resistance 1 - junc- tion to ambient of the 88E8053 device 64-pin qfn package ja = (t j - t a )/ p p = total power dissipation 1. refer to white paper on tj therma l calculations for more information. jedec 3 in. x 4.5 in. 4- layer pcb with no air flow 23.30 c/w jedec 3 in. x 4.5 in. 4- layer pcb with 1 meter/sec air flow 20.60 c/w jedec 3 in. x 4.5 in. 4- layer pcb with 2 meter/sec air flow 19.60 c/w jedec 3 in. x 4.5 in. 4- layer pcb with 3 meter/sec air flow 19.00 c/w jt thermal characteristic parameter 1 - junction to top center of the 88E8053 device 64-pin qfn package jt = (t j - t top )/p. ttop = temperature on the top center of the package jedec 3 in. x 4.5 in. 4- layer pcb with no air flow 0.17 c/w jedec 3 in. x 4.5 in. 4- layer pcb with 1 meter/sec air flow 0.40 c/w jedec 3 in. x 4.5 in. 4- layer pcb with 2 meter/sec air flow 0.50 c/w jedec 3 in. x 4.5 in. 4- layer pcb with 3 meter/sec air flow 0.58 c/w jc thermal resistance 1 - junc- tion to case of the 88E8053 device 64-pin qfn package jc = (t j - t c )/ p to p p to p = power dissipation from the top of the package jedec with no air flow 9.30 c/w jb thermal resistance 1 - junc- tion to board of the 88E8053 device 64-pin qfn package jb = (t j - t b )/ p bottom p bottom = power dissipation from the bottom of the pack- age to the pcb surface. jedec with no air flow 15.50 c/w marvell confidential - for dfi only free datasheet http:///
yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 242 document classification: proprie tary information april 20, 2004, advanced 4.4 dc electrical characteristics 4.4.1 current consumption avddl 4.4.2 current consumption vdd (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ max units i avddl 2.5v power to analog core - copper avddl no link 82 ma 1000 mbps traffic 218 ma 100 mbps traffic 126 ma 10 mbps traffic 108 ma lom_disable without switch 4 ma d3 cold with pme dis- abled without switch 12 ma d3 cold without pme dis- abled without switch 27 ma (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ max units i vdd core power (1.2v) vdd no link 171 ma 1000 mbps traffic 426 ma 100 mbps traffic 203 ma 10 mbps traffic 179 ma lom_disable without switch 13 ma d3 cold with pme dis- abled without switch 29 ma d3 cold without pme dis- abled without switch 130 ma marvell confidential - for dfi only free datasheet http:///
electrical specifications dc electrical characteristics copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 243 4.4.3 current consumption vddo_ttl (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ max units i vddo_ttl pci i/o power (3.3v) vddo_ttl no link 4 ma 1000 mbps traffic 4 ma 100 mbps traffic 4 ma 10 mbps traffic 4 ma lom_disable without switch 3 ma d3 cold with pme dis- abled without switch 3 ma d3 cold without pme dis- abled without switch 3 ma marvell confidential - for dfi only free datasheet http:///
yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 244 document classification: proprie tary information april 20, 2004, advanced 4.4.4 digital operating conditions table 55: 88E8053 internal resistor description (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ max units v ih high level input voltage all pins 2.0 v dd +0.5 v xtali v il low level input voltage all pins -0.5 0.8 v xtali v oh high level output voltage led pins 1 1. the led pins are as follows: led_actn, led_link10/100n, led_link1000n, led_linkn. 2.4 v xtalo v all others (except intan ) 2.4 v v ol low level output voltage led pins 0.4 v xtalo v intan pin v all others 0.4 v i ilk input leakage current with pull-up resistor 0 electrical specifications dc electrical characteristics copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 245 4.4.5 ieee dc transceiver parameters ieee tests are typically based on templates and cannot simply be specified by a number. for an exact description of the template and the test conditions, refer to the ieee specifications: -10base-t ieee 802.3 clause 14 -100base-tx ansi x3.263-1995 (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ max units v odiff absolute peak differential output voltage mdi[1:0] 10base-t no cable 2.2 2.5 2.8 v mdi[1:0] 10base-t cable model 585 1 1. ieee 802.3 clause 14, figure 14.9 shows the template for the ?f ar end? wave form. this template allows as little as 495 mv peak differential voltage at the far end receiver. mv mdi[1:0] 100base-tx mode 0.950 1.0 1.050 v mdi[3:0] 1000base-t 2 2. ieee 802.3ab figure 40 -19 points a&b. 0.67 0.75 0.82 v overshoot 2 mdi[1:0] 100base-tx mode 0 5% v amplitude symmetry (positive/ negative) mdi[1:0] 100base-tx mode 0.98x 1.02x v+/v- v idiff peak differential input voltage mdi[1:0] 10base-t mode 585 3 3. the input test is actually a template test ; ieee 802.3 clause 14, figure 14.17 shows the template for the receive wave form. mv signal detect assertion mdi[1:0] 100base-tx mode 1000 460 4 4. the ansi tp-pmd specification requires that any receiv ed signal with peak-to-peak differential amplitude greater than 1000 mv should turn on signal detect (internal signal in 100base-tx mode). the 88E8053 will accept signals typically with 460 mv peak-to-peak differential amplitude. mv peak- peak signal detect de-assertion mdi[1:0] 100base-tx mode 200 360 5 5. the ansi tp-pmd specification requires that any rece ived signal with peak-to-peak differential amplitude less than 200 mv should de-assert signal detect (internal si gnal in 100base-tx mode). the 88E8053 will reject signals typically with peak-to-peak differ ential amplitude less than 360 mv. mv peak- peak marvell confidential - for dfi only free datasheet http:///
yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 246 document classification: proprie tary information april 20, 2004, advanced 4.5 ac timing reference values symbol parameter pins min typ max units v ih (min.) input high voltage refer- ence 1.9 v v il (max.) input low voltage reference 0.7 v v oh (min.) output high voltage refer- ence 1.9 v v ol (max.) output low voltage refer- ence 0.7 v marvell confidential - for dfi only free datasheet http:///
electrical specifications ac electrical specifications copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 247 4.6 ac electrical specifications 4.6.1 reset timing figure 15: timing requirements from bios (lom_disable starts with low) figure 16: timing requirements from bios (lom_disable starts with high) (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t1 100 ms from pci-express spec. t2 1ms < t2 < 12 ms t3 150 ms t4 5 ms t5 150 ms power perstn lom_disablen t1 t2 t3 t4 t5 power perstn lom_disablen t5 t1 t4 t5 marvell confidential - for dfi only free datasheet http:///
yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 248 document classification: proprie tary information april 20, 2004, advanced 4.6.2 device wakeup timing figure 17: device enable from lom disable state figure 18: device wakeup from power management state (d3 cold) (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units t1 perstn from lom_disablen 150 ms t2 perstn timing 5 ms perstn lom_disablen t1 t2 perstn lom_disablen t1 power (3.3v) marvell confidential - for dfi only free datasheet http:///
electrical specifications ac electrical specifications copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classifi cation: proprietary information page 249 4.6.3 clock timing figure 19: clock timing (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter condition min typ max units t p_xtal xtal period 50 ppm 40 40 40 ns t h_xtal xtal high time 13 20 27 ns t l_xtal xtal low time 13 20 27 ns t r_xtal xtal rise 10% to 90% --3.0ns t f_xtal xtal fall 90% to 10% --3.0ns t p_xtal1 t h_xtal1 t l_xtal1 t r_xtal1 t f_xtal1 xtal marvell confidential - for dfi only free datasheet http:///
yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 250 document classification: proprietary information april 20, 2004, advanced 4.6.4 pci express timing 4.6.4.1 differential transmitter (tx) output specifications (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter min typ max units ui unit interval each ui is 400 ps 300 ppm. ui does not account for ssc dictated variations. 399.88 400 400.12 ps v tx_diffp-p differential peak to peak output voltage v tx_diffp-p =2*iv tx-d+ - v tx-d- i 0.800 1.2 v v tx_de_ratio de-emphasized differential output volt- age (ratio) -3.0 -3.5 -4.0 db t tx-eye minimum tx eye width 0.70 ui t tx-eye-median- to-max-jitter maximum time between the jitter median and maximum deviation from the median 0.15 ui t tx-rise , t tx- fall d+/d- tx output rise/fall time 0.125 ui v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-ch-dc- active-idle- delta absolute delta common mode voltage during l0 and electrical idle 0100mv v tx-cm-dc-line- delta absolute delta of dc common mode volt- age between d+ and d- 025mv v tx-idle-diffp electrical idle differential peak output voltage 020mv v tx-rcv-detect the amount of voltage change allowed during receiver detection 600 mv v tx-dc-cm the tx dc common mode voltage 0 3.6 v i tx-short tx short circuit current limit 90 ma t tx-idle-min minimum time spent in electrical idle 50 ui t tx-idle-set-to- idle maximum time to transition to a valid elec- trical idle after sending an electrical idle ordered set 20 ui t tx-idle-to-to- diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition 20 ui rl tx-diff differential return loss 12 db rl tx-cm common mode return loss 6 db z tx-diff-dc dc differential tx impedance 80 100 120 ? z tx-dc transmitter dc impedance 40 ? c tx ac coupling capacitor 75 200 nf t crosslink crosslink random timeout 0 1 ms marvell confidential - for dfi only free datasheet http:///
electrical specifications ac electrical specifications copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 251 4.6.4.2 differential receiver (rx) output specifications (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter min typ max units ui unit interval 399.88 400 400.12 ps v tx_diffp-p differential peak to peak output voltage v tx_diffp-p =2*iv tx-d+ - v tx-d- i 0.175 1.2 v t rx-eye minimum rx eye width 0.4 ui t rx-eye-median- to-max-jitter maximum time between the jitter median and maximum deviation from the median 0.3 ui v rx-cm-acp ac peak common mode input voltage 150 mv rl rx-diff differential return loss 15 db rl rx-cm tcommon mode return loss 0 3.6 db z rx-diff-dc dc differential input impedance 80 100 120 ? z rx-dc dc input impedance 40 50 60 ? z rx-high-imp-dc powered down dc input impedance 200 k ? v rx-idle-det- diff-p-p electrical idle detect threshold 65 175 mv t rx-idle-det- diff-entertime unexpected electrical idle enter detect threshold integration time 10 ms l rx-skew total skew 20 ns marvell confidential - for dfi only free datasheet http:///
yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 252 document classification: proprietary information april 20, 2004, advanced 4.6.5 two-wire serial interface (twsi) timing figure 20: two-wire se rial interface timing (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter condition min typ max units f twsi_scl scl clock frequency 100 khz 100 khz 400 khz 400 t twsi_ns noise suppression time at scl, sda inputs 100 khz 80 ns 400 khz 80 t twsi_r sda rise time 100 khz 1000 ns 400 khz 300 t twsi_f sda fall time 100 khz 300 ns 400 khz 300 t twsi _ high clock high period 100 khz 4000 ns 400 khz 600 t twsi_lo w clock low period 100 khz 4700 ns 400 khz 1300 t twsi_ su:sta start condition setup time (for a repeated start condi- tion) 100 khz 4700 ns 400 khz 600 t twsi _ hd:sta start condition hold time 100 khz 4000 ns 400 khz 600 t twsi_ su:sto stop condition setup time 100 khz 4000 ns 400 khz 600 t twsi_ su:dat data in setup time 100 khz 250 ns 400 khz 100 t twsi_ hd:dat data in hold time 100 khz 0 ns 400 khz 0 t twsi_buf bus free time 100 khz 4700 ns 400 khz 1300 t twsi_dly scl low to sda data out valid 100 khz 40 200 ns 400 khz 40 200 t twsi_ su:sta t twsi_ hd:sta t twsi_f t twsi_ low t twsi_ high t twsi_ hd:dat t twsi_ su:dat t twsi_ su:sto t twsi_ buf t twsi_r t twsi_dly sda out sda in scl t twsi_f t twsi_r marvell confidential - for dfi only free datasheet http:///
electrical specifications ac electrical specifications copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 253 4.6.6 spi flash memory interface timing (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter min typ max units f sck sck clock frequency 0 20 mhz t ri input rise time 20 ns t fi input fall time 20 ns t wh sck high time 20 ns t wl sck low time 20 ns t cs cs high time 25 ns t css cs setup time 25 ns t csh cs hold time 25 ns t su data in setup time 5 ns t h data in hold time 5 ns t hd hold setup time 15 ns t cd hold time 15 ns t v output valid 20 ns t ho output hold time 0 ns t lz hold to output low z 200 ns t hz hold to output high z 200 ns t dis output disable time 100 ns t ec erase cycle time per sector 1.1 s t bpc byte program cycle time 1 1. the programming time for n bytes will be equal to n * tbpc. 60 100 s endurance 2 2. this parameter is characterized at 3.0v, 25 c and is not 100% tested. 10k write cycles 3 3. one write cycle consists of erasing a sect or, followed by programming the same sector. marvell confidential - for dfi only free datasheet http:///
yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 254 document classification: proprietary information april 20, 2004, advanced figure 21: synchronous data timing t css sck cs v ih v il v ih v il v ih v il v oh v ol t css t csh t wh t wl t su t h t v t ho t dis hi - z hi - z si so marvell confidential - for dfi only free datasheet http:///
electrical specifications ac electrical specifications copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 255 4.6.7 smbus specifications figure 22: smbus ac specifications for an exact description of the smbus 2.0 electrical characteristics, refer to the smbus specification: -system management bus (smbus) specification version 2.0 (over full range of values listed in the recommen ded operating conditions unless otherwise specified) symbol parameter min typ max units f smb smbus operating frequency 10 100 khz t buf bus free time between stop and start con- dition 4.7 s t hd;sta hold time after (repeated) start condi- tion. after this period, the first clock is gen- erated. 4.0 s t su;sta repeated start condition setup 4.7 s t su;sto stop condition after setup time 4.0 s t hd;dat data hold time 300 ns t su;dat data setup time 250 ns t timeout detect clock low timeout 25 35 ms t low clock low period 4.7 s t high clock high period 4.0 50 s t low;sext cumulative clock low extend time (slave device) 25 ms t low;mext cumulative clock low extend time (master device) 10 ms t f clock/data fall time 300 ns t r clock/data rise time 1000 ns t por time in which a device must be opera- tional after power-on reset 500 ms t buf t hd;sta v ih v il v ih v il t r t low t hd;dat t high t f t su;dat t su;sta t su;sto smbclk smbdat marvell confidential - for dfi only free datasheet http:///
yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 256 document classification: proprietary information april 20, 2004, advanced 4.7 ieee ac parameters ieee tests are typically based on templates and cannot simply be specified by number. for an exact description of the templates and the test conditions, refer to the ieee specifications: -10base-t ieee 802.3 clause 14-2000 -100base-tx ansi x3.263-1995 -1000base-t ieee 802.3ab clause 40 section 40.6.1.2 figu re 40-26 shows the template waveforms for transmitter electrical specifications. (over full range of values listed in the recommended operating conditions unless otherwise specified) symbol parameter pins condition min typ max units t rise rise time mdi[1:0] 100base-tx 3.0 4.0 5.0 ns t fall fall time mdi[1:0] 100base-tx 3.0 4.0 5.0 ns t rise / t fall symmetry mdi[1:0] 100base-tx 0 0.5 ns dcd duty cycle distortion mdi[1:0] 100base-tx 0 0.5 1 1. ansi x3.263-1995 figure 9-3. ns, peak- peak transmit jitter mdi[1:0] 100base-tx 0 1.4 ns, peak- peak marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 257 mechanical drawings 64-pin qfn package section 5. mechanical drawings 5.1 64-pin qfn package figure 23: 88E8053 64-pin qfn package (all dimensions in mm) detail : b 0.6max e e2 0.08 c a seating plane "a" d2 c ''b'' aaa e e1 n 3 2 1 aaa c d d1 l a a2 b detail : a 0.6max b a1 a3 x 4 o 1.0mm marvell confidential - for dfi only free datasheet http:///
doc. no. mv-s102130-00, rev. -- confidential copyright ? 2004 marvell page 258 document classification: proprietary information april 20, 2004, advanced yukon? 88E8053 pci express 1.0a-based integrated mac/phy gigabit ethernet controller for lom and nic applications table 56: 64-pin qfn mechanical dimensions dimensions in mm symbol min nom max a 0.80 0.85 1.00 a1 0.00 0.02 0.05 a2 -- 0.65 1.00 a3 0.20 ref b 0.18 0.23 0.30 d 9.00 bsc d1 8.75 bsc e 9.00 bsc e1 8.75 bsc e 0.50 bsc l 0.30 0.40 0.50 0 -- 12 aaa -- -- 0.25 bbb -- -- 0.10 chamfer -- -- 0.60 die pad size symbol dimension in mm d 2 5.46 0.20 e 2 6.25 0.20 marvell confidential - for dfi only free datasheet http:///
copyright ? 2004 marvell confidential doc. no. mv-s102130-00, rev. -- april 20, 2004, advanced document classification: proprietary information page 259 order information section 6. order information figure 24 shows the ordering part numbering scheme for the 88E8053. contact marvell ? or sales representatives for complete ordering information. figure 24: sample ordering part number the standard ordering part number is: ? 88E8053-xx-nnc-c000 figure 25 shows a typical package marking and pin 1 location for an 88E8053 part. markings for the other variants are similar. figure 25: 88E8053 package marking and pin 1 location 88E8053- xx - xxx - c000 - t123 part number package code nnc - 64-pin qfn die revision e.g., a0 = 1st revision temperature range c = commercial speed code custom (optional) 88E8053 88E8053- nnc lot number yyww xx@ country part number and package code date code, die revision, and assembly plant code (contained in the mold id or marked as the last line on the package) pin 1 location logo country of origin date code = yyww die revision = xx assembly plant code = @ marvell confidential - for dfi only free datasheet http:///
us and worldwide offices marvell semiconductor, inc. 700 first avenue sunnyvale, ca 94089 tel: 1.408.222.2500 fax: 1.408.752.9028 marvell asia pte, ltd. 151 lorong chuan, #02-05 new tech park singapore 556741 tel: 65.6756.1600 fax: 65.6756.7600 marvell japan k.k. shinjuku center bldg. 50f 1-25-1, nishi-shinjuku, shinjuku-ku tokyo 163-0650 tel: 81.(0).3.5324.0355 fax: 81.(0).3.5324.0354 marvell semiconductor israel, ltd. moshav manof d.n. misgav 20184 israel tel: 972.4.999.9555 fax: 972.4.999.9574 worldwide sales offices western us sales office marvell 700 first avenue sunnyvale, ca 94089 tel: 1.408.222.2500 fax: 1.408.752.9028 sales fax: 1.408.752.9029 central us sales office marvell 11709 boulder lane, ste. #220 austin, tx 78726 tel: 1.512.336.1551 fax: 1.512.336.1552 eastern us/canada sales office marvell parlee office park 1 meeting house road, suite 1 chelmsford, ma 01824 tel: 978 250-0588 fax: 978 250-0589 europe sales office marvell 3 clifton court corner hall hemel hempstead hertfordshire, hp3 9xy united kingdom tel: 44.(0).1442.211668 fax: 44.(0).1442.211543 marvell fagerstagatan 4 163 08 spanga stockholm, sweden tel: 46.16.146348 fax: 46.16.482425 marvell 5 rue poincare 56400 le bono france tel: 33.297.579697 fax: 33.297.578933 israel sales office marvell ofek center bldg. 2, floor 2 northern industrial zone lod 71293 israel tel: 972.8.924.7555 fax: 972.8.924.7554 china sales office marvell 5j, 1800 zhong shan west road shanghai, china 200233 tel: 86.21.6440.1350 fax: 86.21.6440.0799 japan sales office marvell helios kannai bldg. 12f 3-21-2 motohama-cho, naka-ku yokohama, kanagawa japan 231-0004 tel: 81.45.222.8811 fax: 81.45.222.8812 taiwan sales office marvell 2fl., no. 1, alley 20, lane 407 ti-ding blvd., nei hu district taipei, taiwan 114, r. o. c tel: (886-2).7720.5700 fax: (886-2).7720.5707 copyright ? 2004. marvell international ltd. all rights reserv ed. marvell, the marvell logo, moving forward faster, alaska, fastwriter, galnet, phyadvantage and prestera are registered trademarks of marvell. discovery, dsp switcher, galtis, horizon, libertas, link street, netgx, r adlan, raising the tech- nology bar, the technology within, unimac, virtual cable tester, and yukon are trademarks of marvell. all other trademarks are the property of their re- spective owners. marvell semiconductor, inc. 700 first avenue sunnyvale, ca 94089 phone 408.222.2500 fax 408.752.9028 www.marvell.com for more information, visit our website at: www.marvell.com marvell confidential - for dfi only free datasheet http:///

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